93C46B datasheet(7/24 Pages) MICROCHIP

7 / 24 page

 2003 Microchip Technology Inc.

DS21749D-page 7

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C

2.5

ERASE ALL (ERAL)

The Erase All (ERAL) instruction will erase the entire

memory array to the logical ‘1’ state. The ERAL cycle is

identical to the ERASE cycle, except for the different

opcode. The ERAL cycle is completely self-timed and

commences at the falling edge of the CS, except on

‘93C’ devices where the rising edge of CLK before the

last data bit initiates the write cycle. Clocking of the

CLK pin is not necessary after the device has entered

the ERAL cycle.

The DO pin indicates the READY/BUSY status of the

device, if CS is brought high after a minimum of 250 ns

low (TCSL).

Note:

Issuing a Start bit and then taking CS low

will clear the READY/BUSY status from

DO.

VCC must be

≥ 4.5V for proper operation of ERAL.

FIGURE 2-3:

ERAL TIMING FOR 93AA AND 93LC DEVICES

FIGURE 2-4:

ERAL TIMING FOR 93C DEVICES

CLK

TCSL

CHECK STATUS

•••

TSV

TCZ

BUSY

READY

HIGH-Z

TEC

HIGH-Z

VCC must be

≥ 4.5V for proper operation of ERAL.

CLK

TCSL

CHECK STATUS

•••

TSV

TCZ

BUSY

READY

HIGH-Z

TEC

HIGH-Z

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