AD7452BRTZ-R2 datasheet(5/25 Pages) AD

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AD7452

Data Sheet

Rev. C | Page 4 of 24

Parameter

Test Conditions/Comments

B Version2

Unit

CONVERSION RATE

Conversion Time

1.6 µs with a 10 MHz SCLK

SCLK cycles

Track-and-Hold Acquisition Time3

Sine wave input

200

ns max

Step input

290

ns max

Throughput Rate

555

kSPS max

POWER REQUIREMENTS

Range: 3 V + 20%/–10%;

5 V ± 5%

2.7/5.25

V min/V max

9, 10

Normal Mode (Static)

SCLK on or off

0.5

mA typ

Normal Mode (Operational)

DD = 4.75 V to 5.25 V

1.5

mA max

DD = 2.7 V to 3.6 V

1.2

mA max

Full Power-Down Mode

SCLK on or off

µA max

Power Dissipation

Normal Mode (Operational)

DD = 5 V, 1.55 mW typ for 100 kSPS

7.25

mW max

DD = 3 V, 0.64 mW typ for 100 kSPS

3.3

mW max

Full Power-Down

DD = 5 V, SCLK on or off

µW max

DD = 3 V, SCLK on or off

µW max

1 Common-mode voltage. The input signal can be centered on a dc common-mode voltage in the range specified in Figure 23 and Figure 24.

2 Temperature ranges as follows: B Version: –40°C to +85°C.

3 See Terminology section.

4 Analog inputs with slew rates exceeding 27 V/µs (full-scale input sine wave > 3.5 MHz) within the acquisition time may cause an incorrect result to be returned by the

converter.

5 Because the input spans of V

IN+ and VIN– are both VREF and are 180° out of phase, the differential voltage is 2 × VREF.

6 The AD7452 is functional with a reference input from 100 mV; for V

DD = 5 V, the reference can range up to 3.5 V.

7 The AD7452 is functional with a reference input from 100 mV; for V

DD = 3 V, the reference can range up to 2.2 V.

8 Guaranteed by characterization.

9 See Power VS. Throughput Rate section.

10 Measured with a midscale dc input.

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