AD7452BRTZ-R2 datasheet(22/25 Pages) AD

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Data Sheet

AD7452

Rev. C | Page 21 of 24

POWER-UP TIME

The power-up time of the AD7452 is typically 1 μs, which

means that with any SCLK frequency up to 10 MHz, one

dummy cycle is always sufficient to allow the device to power

up. Once the dummy cycle is complete, the ADC is fully

powered up and the input signal will be acquired properly. The

quiet time, tQUIET, must still be allowed from the point at which

the bus goes back into three-state after the dummy conversion

to the next falling edge of CS.

When running at the maximum throughput rate of 555 kSPS,

the AD7452 powers up and acquires a signal within ±0.5 LSB in

one dummy cycle. When powering up from the power-down

mode with a dummy cycle, as in Figure 38, the track-and-hold,

which was in hold mode while the part was powered down,

returns to track mode after the first SCLK edge the part receives

after the falling edge of CS. This is shown as Point A in

Figure 38.

Although at any SCLK frequency one dummy cycle is sufficient

to power up the device and acquire VIN, it does not necessarily

mean that a full dummy cycle of 16 SCLKs must always elapse

to power up the device and acquire VIN fully; 1 μs is sufficient to

power up the device and acquire the input signal.

For example, if a 5 MHz SCLK frequency is applied to the ADC,

the cycle time is 3.2 μs (that is, 1/(5 MHz) × 16). In one dummy

cycle, 3.2 μs, the part is powered up and VIN fully acquired.

However, after 1 μs with a 5 MHz SCLK, only five SCLK cycles

would have elapsed. At this stage, the ADC is fully powered up

and the signal acquired. So in this case, CS can be brought high

after the 10th SCLK falling edge and brought low again after a

time, tQUIET, to initiate the conversion.

When power supplies are first applied to the AD7452, the ADC

may power up either in power-down mode or in normal mode.

Because of this, it is best to allow a dummy cycle to elapse to

ensure the part is fully powered up before attempting a valid

conversion. Likewise, if the user wants the part to power up in

power-down mode, the dummy cycle may be used to ensure the

device is in power-down by executing a cycle such as the one

shown in Figure 37.

Once supplies are applied to the AD7452, the power-up time is

the same as that when powering up from power-down mode. It

takes approximately 1 μs to power up fully if the part powers up

in normal mode. It is not necessary to wait 1 μs before

executing a dummy cycle to ensure the desired mode of

operation. Instead, the dummy cycle can occur directly after

power is supplied to the ADC. If the first valid conversion is

performed directly after the dummy conversion, care must be

taken to ensure that adequate acquisition time has been

allowed.

As mentioned earlier, when powering up from the power-down

mode, the part returns to track mode upon the first SCLK edge

applied after the falling edge of CS. However, when the ADC

powers up initially after supplies are applied, the track-and-hold

is already in track mode. This means if (assuming one has the

facility to monitor the ADC supply current) the ADC powers

up in the desired mode of operation, and thus a dummy cycle is

not required to change the mode, and a dummy cycle is not

required to place the track-and-hold into track mode.

SCLK

SDATA

THIS PART IS FULLY POWERED

UP WITH VIN FULLY ACQUIRED

PART BEGINS

TO POWER UP

INVALID DATA

VALID DATA

tPOWER-UP

Figure 38. Exiting Power-Down Mode

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