AD7452BRTZ-R2 datasheet(23/25 Pages) AD

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AD7452

Data Sheet

Rev. C | Page 22 of 24

POWER vs. THROUGHPUT RATE

By using the power-down mode on the AD7452 when not con-

verting, the average power consumption of the ADC decreases

at lower throughput rates. Figure 39 shows how, as the through-

put rate is reduced, the device remains in its power-down state

longer and the average power consumption is reduced

accordingly. It shows this for both 5 V and 3 V power supplies.

For example, if the AD7452 is operated in continuous sampling

mode with a throughput rate of 100 kSPS and an SCLK of

10 MHz, and the device is placed in power-down mode between

conversions, the power consumption is calculated as follows:

Power Dissipation during Normal Operation = 7.25 mW max

(for VDD = 5 V)

If the power-up time is one dummy cycle (1.06 µs if CS is

brought high after the 10th SCLK falling edge and then brought

low after the quiet time) and the remaining conversion time is

another cycle, that is, 1.6 µs, the AD7452 can be said to dissipate

7.25 mW for 2.66 µs during each conversion cycle. This 2.66 µs

figure assumes a very short time to enter power-down mode.

This increases as the burst of clocks used to enter the power-

down mode is increased.

If the throughput rate = 100 kSPS, the cycle time = 10 µs and

the average power dissipated during each cycle is

(2.66/10) × 7.25 mW = 1.92 mW

For the same scenario, if VDD = 3 V, the power dissipation

during normal operation is 3.3 mW max.

The AD7452 can now be said to dissipate 3.3 mW for 2.66 µs

during each conversion cycle. This 2.66 µs figure assumes a very

short time to enter power-down mode. This increases as the

burst of clocks used to enter the power-down mode is increased.

The average power dissipated during each cycle with a

throughput rate of 100 kSPS is therefore

(2.66/10) × 3.3 mW = 0.88 mW

This is how the power numbers in Figure 39 are calculated.

For throughput rates above 320 kSPS, it is recommended that

the serial clock frequency be reduced for optimum power

performance.

THROUGHPUT (kSPS)

100

350

0.01

100

150

200

250

300

0.1

VDD = 5V

VDD = 3V

Figure 39. Power vs. Throughput Rate for Power-Down Mode

APPLICATION HINTS

Grounding and Layout

The printed circuit board that houses the AD7452 should be

designed so that the analog and digital sections are separated

and confined to certain areas of the board. This facilitates the

use of ground planes that can be easily separated. A minimum

etch technique is generally best for ground planes as it gives the

best shielding. Digital and analog ground planes should be

joined in only one place, a star ground point established as close

as possible to the GND pin on the AD7452. Avoid running

digital lines under the device because this couples noise onto

the die. The analog ground plane should be allowed to run

under the AD7452 to avoid noise coupling. The power supply

lines to the AD7452 should use as large a trace as possible to

provide low impedance paths and reduce the effects of glitches

on the power supply line.

Fast switching signals like clocks should be shielded with digital

ground to avoid radiating noise to other sections of the board,

and clock signals should never run near the analog inputs.

Avoid crossover of digital and analog signals. Traces on

opposite sides of the board should run at right angles to each

other. This reduces the effects of feedthrough through the

board. A micro-strip technique is by far the best but is not

always possible with a double-sided board.

In this technique, the component side of the board is dedicated

to ground planes while signals are placed on the solder side.

Good decoupling is also important. All analog supplies should

be decoupled with 10 µF tantalum capacitors in parallel with

0.1 µF capacitors to GND. To achieve the best from these

decoupling components, place them as close to the device as

possible.

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