STLC2415 datasheet(10/22 Pages) STMICROELECTRONICS

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STLC2415

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Table 9. Pin List (continued)

Name

Pin #

Description

DIR

PU/PD

VDD

PAD

To be connected together on the PCB’s top layer

Flash chip enable

csn0

External chip select bank 0

Test Only (Do NOT connect)

rdn/ng

External read

CMOS 1.8V

4mA

slew rate control

csn1

External chip select bank 1

csn2

External chip select bank 2

addr0

External address bit 0

addr2

External address bit 2

addr17

External address bit 17

addr18

External address bit 18

addr19

External address bit 19

data0

External data bit 0

I/O

data1

External data bit 1

I/O

data2

External data bit 2

I/O

data3

External data bit 3

I/O

data4

External data bit 4

I/O

data5

External data bit 5

I/O

data6

External data bit 6

I/O

CMOS 1.8V

4mA

slew rate control

data7

External data bit 7

I/O

data8

External data bit 8

I/O

data9

External data bit 9

I/O

data10

External data bit 10

I/O

data11

External data bit 11

I/O

data12

External data bit 12

I/O

data13

External data bit 13

I/O

data14

External data bit 14

I/O

data15

External data bit 15

I/O

Not Connected

n.c.

C16,

G3,

N3,

Not Connected

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