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STLC2415

4

PINOUT

Figure 3. Pinout (Bottom view)

4.1 Pin Description and Asthe signment

Table 9 shows the pin list of STLC2415. There are 91 functional pins of which 25 are used for device test-

ing only (should not be connected in the application) and 24 supply pins. The column "PU/PD" shows the

pads implementing an internal weak pull-up/down, to fix value if the pin is left open. This can not replace

an external pull-up/down.

The pads are grouped according to two different power supply values, as shown in column "VDD":

– V1 for 3.3 V typical 2.7 - 3.6 V range

– V2 for 1.8 V typical 1.55 - 1.95 V range

Finally the column "DIR" describes the pin directions:

– I for inputs

– O for outputs

– I/O for input/outputs

– O/t for tristate outputs

D03TL583

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

V

14

13

12

11

18

17

16

15

10

9

8

7

6

5

4

3

2

1

i2c_

dat

i2c_

clk

pcm_

sync

pcm_

a

nreset

nrp

uart1_

rxd

uart1_

txd

usb_

dn

uart2_

rxd

uart2_

txd

uart2_

i1

uart2_

o2

vddio

vdd

vss

spi_

frm

spi_

clk

xin

int2

int1

vddio

n.c.

vssio

tck

vssio

tdo

tms

ntrst

tdi

btxen

ne

csn2

rdn/ng

csn1

addr0

vddio

sys_cl

k_req

brxen

addr2

nwp

vdd

vss

vpp

ant_sw

bpktcl

btxd

bpaen

bdclk

vddf

bmosi

brclk

vssf

addr17

vss

n.c.

vdd

pcm_

clk

pcm-

b

usb_

dp

uart2_

i2

uart2_

o1

uart2_

io1

uart2_

io2

vssio

brxd

bmiso

data3

data1

n.c.

n.c.

data0

addr19

vddq

csn0

spi_rxd

addr18

bsen

bnden

gpio3 gpio1

boot

vss

vdd

data8 data7 data6 data5 data4

gpio12

gpio14

gpio15

gpio10

gpio11

gpio13

gpio9

vddpll

gpio8 gpio7 gpio6

gpio2 gpio0

vddio

vsspll

gpio4

vssio

gpio5

lpo_

clk_n

lpo_

clk_p data15 data14 data13 data12 data11 data10 data9

data2

vss

vdd

spi_txd