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STLC2415

including internal decimator and interpolator filters. The data can be linear PCM (13-16bit), µ-Law (8bit) or

A-Law (8bit). By default the codec interface is configured as master. The encoding on the air interface is

programmable to be CVSD, A-Law or µ-Law.

The PCM block is able to manage the PCM bus with up to 3 timeslots.

In master mode, PCM clock and data can operate at 2 MHz or at 2.048 MHz to allow interfacing of stan-

dard codecs.

The four signals of the PCM interface are:

– PCM_CLK : PCM clock

– PCM_SYNC : PCM 8kHz sync

– PCM_A : PCM data

– PCM_B : PCM data

Directions of PCM_A and PCM_B are software configurable.

Figure 6. PCM (A-law,

µ-law) Standard Mode

Figure 7. Linear Mode

Table 11. PCM Interface Timing.

Symbol

Description

Min

Typ

Max

Unit

PCM Interface

Frequency of PCM_CLK (master)

-

2048

kHz

Frequency of PCM_SYNC

8

kHz

High period of PCM_CLK

200

ns

Low period of PCM_CLK

200

ns

High period of PCM_SYNC

200

ns

Setup time, PCM_SYNC high to PCM_CLK low

100

ns

Setup time, PCM_A/B input valid to PCM_CLK low

100

ns

Hold time, PCM_CLK low to PCM_A/B input invalid

100

ns

Delay time, PCM_CLK high to PCM_A/B output valid

150

ns

D02TL558

PCM_CLK

PCM_SYNC

PCM_A

B

B

PCM_B

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

B

125

µs

B

D02TL559

PCM_CLK

PCM_SYNC

PCM_A

PCM_B

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

125

µs