STLC2415

4/22

Figure 2. Block Diagram and Electrical Schematic

RADIO

I/F

BLUETOOTH

CORE

ARM7

TDMI

APB

BRIDGE

INTERRUPT

CONTROLLER

TIMER

START

DETECT

UART

FIFO

SYSTEM

CONTROL

EMI

DATA(0..15)

ADDR(0..19)

CSN(0)

WRN

RDN

NW

NG

NE

ADDR(1..18)

DATA(0..15)

4Mbit

FLASH

UART

UART

100nF

100nF

22pF

Y2

32KHz

(*) If a low-power clock is available, it can be connected to the LPOCLKP pin in stead of using a crystal

(**) For device testing only (should not be connected in the application.

22pF

GPIO

BOOT

ROM

D

M

A

RAM

LPO

13

4

RF BUS

PCM

EXT._INT1/2

USB

SPI

GPIO(O..15)

UART2

UART1

NRESET

SYS_CLK_REQ

LPOCLKP

LPOCLKN

VDDPLL

SPI

USB

PCM

2

2

4

1

5

JTAG

XIN

BOOT

CSN(1..2)

RDN/NG

NRP

NWP

CSN(0)

NE

ADDR

(0,2,17,18,19)

DATA(0..15)

2

1

1

1

20

18

16

16

16

8

2

2

2

1

1

5

D03TL582A

100nF

100nF

100nF

(*)

(**)

16