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CS53L32A 数据表(PDF) 15 Page - Cirrus Logic |
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CS53L32A 数据表(HTML) 15 Page - Cirrus Logic |
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15 / 40 page ![]() CS53L32A DS513F1 15 3. REGISTER QUICK REFERENCE ** “default” ==> bit status after power-up-sequence or reset. 3.1 I/O and Power Control (address 01h) BOOST 20 dB Digital Gain Default = ‘0’ 0 - Disabled 1 - Enabled AINMUX Analog Input Multiplexer Default =’0’. 0 - AIN_L1/AIN_R1 direct to A/D (default) 1 - AIN_L2/AIN_R2 direct to A/D 2 - AIN_L2/AIN_R2 through PGA to A/D 3 - Reserved PDN Power-Down Default =’1’. 0 - Disabled 1 - Enabled CP_EN Control Port Enable Default =’0’. 0 - Disabled 1 - Enabled 3.2 Interface Control (address 02h) MCLKDIV Master Clock Divider Default =’0’. 0 - Disabled 1 - Enabled RATIO1-0 Master Clock Ratio Default =’0’. 0 - 128x (default) 1 - 192x 2 - 256x 3 - 384x MASTER Master Mode Default =’0’. 0 - Slave Mode 1 - Master Mode 76543 210 RESERVED BOOST AINMUX1 AINMUX0 RESERVED RESERVED PDN CP_EN 00000 010 76543 210 RESERVED MCLKDIV RATIO1 RATIO0 MASTER DIF2 DIF1 DIF0 00000 000 |
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