CS53L32A

DS513F1

21

4.7

MASTER MODE

Interface Control Register (address 02h)

Access:

R/W in Two Wire Mode and write only in SPI.

Default:

0 - Slave Mode

Function:

Configures the device for master or slave operation when in Control Port mode.

4.8

DIGITAL INTERFACE FORMAT

Interface Control Register (address 02h)

Access:

R/W in Two Wire Mode and write only in SPI.

Default:

Function:

The required relationship between the Left/Right clock, serial clock and serial data is defined by the

Digital Interface Format and the options are detailed in Figures 18 through 21.

76543

210

RESERVED

MCLKDIV

RATIO1

RATIO0

MASTER

DIF2

DIF1

DIF0

MASTER

MODE

0

Slave Mode

1

Master Mode

Table 6. Master/Slave Mode Selection

7654

3

210

RESERVED

MCLKDIV

RATIO1

RATIO0

MASTER

DIF2

DIF1

DIF0

DIF2 DIF1 DIF0

DESCRIPTION

Format

FIGURE

00

0

018

0

0

1

Left Justified, up to 24-bit Data, Data valid on positive edge of SCLK

1

19

0

1

0

Reserved

2

-

0

1

1

Right Justified, 16-bit Data, Data valid on positive edge of SCLK

3

18

1

0

0

Right Justified, 24-bit Data, Data valid on positive edge of SCLK

4

19

1

0

1

Right Justified, 18-bit Data, Data valid on positive edge of SCLK

5

20

1

1

0

Right Justified, 20-bit Data, Data valid on positive edge of SCLK

6

21

1

1

1

Reserved

7

-

Table 7. Digital Interface Format