CS53L32A datasheet(27/40 Pages) CIRRUS

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CS53L32A

DS513F1

PIN DESCRIPTION

Interface Power

RST

Reset

Master Clock

MCLK

Quiescent Voltage

Serial Clock

SCLK

AIN_L1

Analog Input 1 Left

Serial Audio Data Out

SDOUT

AIN_R1

Analog Input 1 Right

Analog Power

REF_GND

Reference Ground

Ground

GND

AIN_L2

Analog Input 2 Left

Left/Right Clock

LRCK

AIN_R2

Analog Input 2 Right

AD0/CS/DIV

FILT+

Positive Voltage Reference

SDA/CDIN/DIF

AFLTL

Anti-Aliasing Capacitor

SCL/CCLK/ChSEL SCL/CCLK/ChSEL

AFLTR

Anti-Aliasing Capacitor

Interface Power

(

Input) - Digital interface power supply. Typically 1.8 to 3.3 VDC.

Master Clock

MCLK

(

Input) - The master clock frequency must be either 256x, 384x,

512x, 768x or 1024x the input sample rate in Base Rate Mode (BRM) and

128x, 192x, 256x, 384x the input sample rate in High Rate Mode (HRM).

Table 16 illustrates several standard audio sample rates and the required

master clock frequencies.

Serial Clock

SCLK

(

Input/Output) - Clocks the individual bits of the serial data out of the

SDOUT pin. The required relationship between the Left/Right clock, serial

clock and serial data is defined by the DIF2-0 bytes when in Control Port

mode or by the DIF1-0 pins when in Stand-Alone mode.

Serial Audio Data Out

SDOUT

(

Output) - This pin serves two functions.

First: Two's complement MSB-first serial data is output on this pin. The data

is clocked out of SDOUT via the serial clock and the channel is determined

by the Left/Right clock. The required relationship between the Left/Right

clock, serial clock and serial data is defined by the DIF2-0 bytes when in

Control Port mode or by the DIF pin when in Stand-Alone mode.

Second: In Stand-alone mode, Master/Slave mode selection is determined,

at start-up, by a 47 kOhm pull-up/pull-down on this line. A pull-up to VL

selects Master mode and a pull-down to GND selects Slave mode.

Analog Power

(

Input) - Analog power supply. Typically 1.8 to 3.3 VDC.

Ground

GND

(

Input) - Ground Reference.

Left/Right Clock

LRCK

(

Input/Output) - The Left/Right clock determines which channel is cur-

rently being output on the serial audio data line SDOUT. The frequency of

the Left/Right clock must be at the input sample rate. The required relation-

ship between the Left/Right clock, serial clock and serial data is defined by

the DIF2-0 bytes when in Control Port mode or by the DIF pin when in

Stand-Alone mode.

CS53L32A 数据表(PDF) 27 Page - Cirrus Logic

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