L9678P datasheet(50/203 Pages) STMICROELECTRONICS

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SPI interface

L9678P, L9678P-S

50/203

DocID029274 Rev 3

6ERSTATE

Set when Power mode state machine is in ER state

0 Power mode state machine is not in ER state

1 Power mode state machine is in ER state

5POWERFLT

Fault present in Power State Register, logical OR between bits from 18 to

9 of POWER_STATE Register

0 All the bits from 18 to 9 in the POWER_STATE Registers are 0s

1 At least one of the bits from 18 to 9 in the POWER_STATE Registers is 1

4FLT

Fault present in Fault Status Register (FLTSR), logical OR between all bits

of FLTSR

0 All the bits in the Fault Status Register (FLTSR) are 0s

1 At least one of the bits in the Fault Status Register (FLTSR) is 1

CONVRDY2

ADC Conversion of request 3 or 4 has been completed so new results are

available

0 No new data available

1 New data available

CONVRDY1

ADC Conversion of request 1 or 2 has been completed so new results are

available

0 No new data available

1 New data available

ERR_WID

Write address of previous SPI frame is not permitted in current operating

phase (INIT, DIAG, SAFING, SCRAP, ARMING)

0 No Error

1 Error

ERR_RID

Read address received in the actual SPI frame is unused so data in the

response is don't care

0 No Error

1 Error

Table 7. Global status word (GSW) (continued)

Bit

Name

POR WSM SSM

Description

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