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L9678P 数据表(PDF) 51 Page - STMicroelectronics |
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L9678P 数据表(HTML) 51 Page - STMicroelectronics |
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51 / 203 page  DocID029274 Rev 3 51/203 L9678P, L9678P-S SPI interface 202 Read/write register 5.1.1 Fault status register (FLTSR) Address: 00 Type: R Buffer: $0000 Reset: - 19 18 17 16 15 14 13 12 11 10 9876543 210 MOSI - XXXXXXXX XXXXXXXX MISO 00 -0 0 0 000 0 0 EBST_OT 0 - - ER Boost over-temperature bit Set when over-temp condition detected, cleared on SPI read or POR=1 0 No Fault 1 Fault CLKFRERR 0 - - Internal oscillator cross-check error bit Set when osc error detected, cleared on SPI read or POR=1 0 No Fault 1 Fault OTPCRC_ERR 0 - - OTP CRC error bit Set when OTP error detected (tested at release of POR), cleared by POR=1 0 No Fault 1 Fault WD1_LO 0 0 - WD1 lockout - reflects WD1 lockout state Set and cleared per Watchdog Timer Flow Diagram 0 WD1 Lockout inactive 1 WD1 Lockout active WD1_TM 0 0 0 WD1 test mode - reflects WD1TM signal state Set and cleared per Watchdog Timer Flow Diagram 0 WD1TM=0 1 WD1TM=1 |
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