 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
L9678P 数据表(PDF) 69 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
L9678P 数据表(HTML) 69 Page - STMicroelectronics |
|
|
69 / 203 page  DocID029274 Rev 3 69/203 L9678P, L9678P-S SPI interface 202 5.1.16 WD1 timer control register (WD1T) Address: 2B Type: W Buffer: $2B00 Reset: $0056 5.1.17 WD1 state register (WDSTATE) Address: 2C Type: R Buffer: $2C00 Reset: - 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MOSI - X X X X X X X X X X X X X X WD1CTL[1:0] MISO 0 0 0 0 WD1_TIMER 0 0 0 0 0 0 WD1CTL[1:0] WD1CTL[1:0] 00 00 00 WD1 Control command Updated by SSM_RESET or SPI write 00 NOP 01 Code 'A' 10 Code 'B' 11 NOP WD1_TIMER $00 $00 $00 WD1 Window timer value Cleared by SSM_RESET or by WD1 refresh, incremented every 8µs or 64µs while in WD1_RUN or WD1_TEST states 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MOSI - X X X X X X X X X X X X X X X X MISO 0 0 0 0 0 WD1_ERR_CNT[3:0] WD_STATE[2:0] 0 0 0 0 0 0 0 0 WD1_ERR_CNT[3:0] 000 000 - Watchdog error counter Updated according to Watchdog State Diagram WD1_STATE[2:0] 000 000 - Watchdog state Updated according to Watchdog State Diagram 000 INITIAL |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
