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L9678P 数据表(PDF) 135 Page - STMicroelectronics |
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L9678P 数据表(HTML) 135 Page - STMicroelectronics |
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135 / 203 page  DocID029274 Rev 3 135/203 L9678P, L9678P-S Watchdog timer 202 Figure 37. Watchdog timer refresh diagram 8.2 Watchdog reset assertion timer Upon a watchdog reset, the watchdog logic will momentarily assert the RESET pin for time duration twdrst. When the RESET pin has been asserted through the watchdog reset assertion timer, stored faults are maintained and can be read by the microcontroller via SPI following the RESET period. 8.3 Watchdog timer disable input (WDT/TM) This input pin has a passive pull-down and is used to disable the watchdog timer. The state of this pin can be read by SPI through the WDTDIS_S bit in the GSW register. When WDT/TM pin is asserted, the watchdog timer is disabled, the timer is reset to its starting value and no faults are generated. |
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