SPWF04SA, SPWF04SC

Host interfaces

DocID029757 Rev 5

15/27

Figure 3: SPI connection with host device

Table 7: SPI signals

SPWF04S signal name

Description

RTS/Clk

Clock (up to 22 MHz) from MCU to SPWF04S

CTS/nCS

Active Low indicates the selection of the slave

before a data transmission from the Master

GPIO[9] (nHostInt)

nHostInt. Interrupt sent from the SPWF04S to

the host to indicate the transmission of data

from the slave

RXD/MOSI

Data from Host to SPWF04S

TXD/MISO

Data from SPWF04S to the Host

The host SPI can work up to the speed of 22 MHz. The communication between host and

SPWF04S is handled in half duplex.

Data is transmitted and received with the most significant bit first (SPI mode 0). That

means the clock polarity (CPOL) and the clk phase (CPHA) used to configure SPI are both

set to zero. The mode 0 is commonly used as default for microcontrollers.

Figures from Figure 4: "Single 1 byte transaction" to Figure 6: "RX master transaction"

detail the signaling over the SPI. In particular, Figure 4: "Single 1 byte transaction" shows a

its value depends on the host clock frequency. SPI data is latched by the master and slave

using the CLK signal. So, when data needs to be transferred, the MISO and MOSI signals

change between each clock. After each single request sent from master to the slave, the

Master MUST wait for a confirmation message sent from the slave. The message is notified

to the master using the nHost Irq. All the data transferred in both directions are packed

using a well defined packet format described in the user manual.