Host interfaces

SPWF04SA, SPWF04SC

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DocID029757 Rev 5

Figure 4: Single 1 byte transaction

The Figure 5: "TX master transaction" and Figure 6: "RX master transaction" show a

Master TX transaction and a Master RX transaction, respectively. The communication

starts with the host sending the write SYNC word (0x02), followed by header information,

and then payload, when applicable. Once the command has been analyzed by the device,

it asserts the IRQ interrupt line. Then the host detects the interrupts and then writes the

read SYNC word (0x02) and starts to generate the clock. The device then clears the

interrupt line and prepares the response. The host then reads continuously until the SYNC

pattern is detected. All data until that point is discarded. The SYNC word is then followed

by headers and then payload, when applicable.

Figure 5: TX master transaction

Figure 6: RX master transaction