HT85F2250 datasheet(66/187 Pages) HOLTEK

66 / 187 page

Rev. 1.10

66 of 187

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A/D Flash 8051 Core Low Pin Count MCU

HT85F2250/HT85F2262

Watchdog Registers

There are several registers for overall watchdog timer operation. The WDTREL register is used to

setup the reload value of the Watchdog Timer. The remaining four registers are control registers

which setup the operating and control function of the WDT function. The WDTCR register

controls the WDT enable/disable operation, software reset and clock source select functions. The

WDT and SWDT bits, located in the IEN0 and IEN1 registers respectively, are used to refresh the

WDT counter to prevent the WDT overflow and reset the device. The WDTS bit in the IP0 register

is used to indicate that a WDT software reset has been generated. For details regarding the WDT

software reset function, refer to the datasheet Reset section for details.

WDT Register Contents

Name

Bit

IEN0

(EAL)

WDT

(ET�)

(ES0)

(ET1)

(EX1)

(ET0)

(EX0)

IEN1

(EXEN�)

SWDT

—

(ECMP)

(ECCU�)

(ECCU1)

(ECCU0)

WDTREL

D�

WDTCR

WE4

WE�

WE1

WE0

—

WDTCS

IP0

—

WDTS

(PT�)

(PS0)

(PT1)

(PX1)

(PT0)

(PX0)

Note: The bit and flag names in brackets are used to manage other functions and not related to the

WDT contro�.

IEN0 Register

SFR Address: A8h

Bit

Name

EAL

WDT

ET�

ES0

ET1

EX1

ET0

EX0

R/W

POR

Bit 7

EAL: Master interrupt global enable

Described elsewhere

Bit 6

WDT: Watchdog timer refresh flag

Setting this bit to “1” is the first step in initiating a Watchdog Timer refresh action. The

WDT bit must be set directly before setting the SWDT bit in the IEN1 register. The

two instructions should be executed consecutively and not have any other instruction in

between to prevent an unintentional watchdog timer refresh. This bit will be cleared by

hardware automatically. This bit is always read as “0”.

Bit 5

ET2: Timer 2 interrupt enable

Described elsewhere

Bit 4

ES0: UART 0 interrupt enable

Described elsewhere

Bit 3

ET1: Timer 1 overflow interrupt enable

Described elsewhere

Bit 2

EX1: External interrupt 1 enable

Described elsewhere

Bit 1

ET0: Timer 0 overflow interrupt enable

Described elsewhere

Bit 0

EX0: External interrupt 0 enable

Described elsewhere

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