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TPS54873PWP 数据表(PDF) 9 Page - Texas Instruments

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部件名 TPS54873PWP
功能描述  4-V TO 6-V INPUT, 8-A OUTPUT SYNCHRONOUS BUCK SWITCHER WITH DISABLED SINKING DURING START-UP
PDF  15 Pages
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

TPS54873PWP 数据表(HTML) 9 Page - Texas Instruments

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TPS54873
SLVS444 – OCTOBER 2002
www.ti.com
9
OPERATING FREQUENCY
In the application circuit, the RT pin is grounded through a
71.5-k
Ω resistor (R6) to select the operating frequency of
700 kHz. To set a different frequency, place a 68-k
Ω to
180-k
Ω resistor between RT (pin 28) and analog ground or
leave RT floating to select the default of 350 kHz. The
resistance can be approximated using the following
equation:
R
+
500 kHz
Switching Frequency
100 [k
W]
OUTPUT FILTER
The output filter is composed of a 0.65-
µH inductor (L1)
and 3 x 22-
µF capacitors (C5, C7 and C8). The inductor is
a low dc resistance (.017
Ω) type, Pulse PA0277 0.65 µH.
The capacitors used are 22-
µF, 6.3-V ceramic types with
X5R dielectric. An additional high frequency bypass
capacitor, C13 is also used.
PRECHARGE CIRCUIT
VIN precharges the output of the application circuit
through series diodes (D1 and D2) during start-up. As the
input voltage increases at start-up, the output is
precharged to VIN minus the forward bias voltage of the
two diodes. When the internal reference has ramped up to
a value greater than the voltage fed back to the VSENSE
pin, the output of the internal error amplifier begins to
increase. When this output reaches the maximum ramp
amplitude, the output of the PWM comparator reaches 100
percent duty cycle and the internal logic enables the
high-side FET driver and switching begins. The output
tracks the internal reference until the preset output voltage
is reached. Under no circumstances should the precharge
voltage be allowed to increase above the preset output
value.
GROUNDING AND POWERPAD LAYOUT
The TPS54873 has two internal grounds (analog and
power). Inside the TPS54873, the analog ground ties to all
of the noise sensitive signals, while the power ground ties
to the noisier power signals. The PowerPAD must be tied
directly to AGND. Noise injected between the two grounds
can degrade the performance of the TPS54873,
particularly at higher output currents. However, ground
noise on an analog ground plane can also cause problems
with some of the control and bias signals. For these
reasons, separate analog and power ground areas are
recommended. The analog ground area should be tied to
the power ground area directly at the IC to reduce noise
between the two grounds. The only components that
should tie directly to the power ground area are the input
capacitor, the output capacitor, the input voltage
decoupling capacitor, and the PGND pins of the
TPS54873. The power ground areas as well as the
PowerPAD mounting area should be tied to any internal
ground planes using multiple vias. The layout of the
TPS54873 evaluation module is representative of a
recommended layout for a 4-layer board with the two
internal layers representing the system ground plane.
Documentation for the TPS54873 evaluation module can
be found on the Texas Instruments web site under the
TPS54873 product folder.
LAYOUT CONSIDERATIONS FOR THERMAL
PERFORMANCE
For operation at full rated load current, the analog ground
plane must provide adequate heat dissipating area. A 3
inch by 3 inch plane of 1 ounce copper is recommended,
though not mandatory, depending on ambient temperature
and airflow. Most applications have larger areas of internal
ground plane available, and the PowerPAD should be
connected to the largest area available. Additional areas
on the top or bottom layers also help dissipate heat, and
any area available should be used when 6 A or greater
operation is desired. Connection from the exposed area of
the PowerPAD to the analog ground plane layer should be
made using 0.013 inch diameter vias to avoid solder
wicking through the vias. Eight vias should be in the
PowerPAD area with four additional vias located under the
device package. The size of the vias under the package,
but not in the exposed thermal pad area, can be increased
to 0.018. Additional vias beyond the ten recommended
that enhance thermal performance should be included in
areas not under the device package.
(1)



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