TPS54873

SLVS444 – OCTOBER 2002

www.ti.com

11

Figure 14

–20

0

20

40

60

100

1 k

10 k

100 k

1 M

0

45

90

135

180

f – Frequency – Hz

LOOP RESPONSE

Phase

Gain

VI = 5 V,

VO = 3.3 V,

IO = 6 A,

TA = 25°C,

FS = 550 kHz

Figure 15

25

35

45

55

65

75

85

95

105

115

125

0

123

4

AMBIENT TEMPERATURE

vs

OUTPUT CURRENT

IO – Output Current – A

56

7

8

VI = 5 V

TJ = 25°C

fs = 700 kHz

Figure 16

Time – 1

µs/div

OUTPUT RIPPLE VOLTAGE

Figure 17

100

µs/div

LOAD TRANSIENT RESPONSE

VI = 5 V,

1A to 5A,

Figure 18

5.0 ms/div

START-UP WAVEFORM

VO = 3.3 V

VI = 5 V

DETAILED DESCRIPTION

DISABLED SINKING DURING START-UP

(DSDS)

The DSDS feature enables minimal voltage drooping of

output precharge capacitors at start-up. The TPS54873

is designed to disable the low-side MOSFET to prevent

sinking current from a precharge output capacitor during

start-up. Once the high-side MOSFET has been turned on

to the maximum duty cycle limit, the low-side MOSFET is

allowed to switch. Once the maximum duty cycle condition

is met, the converter functions as a sourcing converter until

the SS/ENA is pulled low.

UNDERVOLTAGE LOCK OUT (UVLO)

The TPS54873 incorporates an under voltage lockout

circuit to keep the device disabled when the input voltage

(VIN) is insufficient. During power up, internal circuits are

held inactive until VIN exceeds the nominal UVLO

threshold voltage of 3.8 V. Once the UVLO start threshold

is reached, device start-up begins. The device operates

until VIN falls below the nominal UVLO stop threshold of

3.5 V. Hysteresis in the UVLO comparator and a 2.5-

µs

rising and falling edge deglitch circuit reduce the likelihood

of shutting the device down due to noise on VIN.

SLOW-START/ENABLE (SS/ENA)

The slow-start/enable pin provides two functions. First, the

pin acts as an enable (shutdown) control by keeping the

device turned off until the voltage exceeds the start

threshold voltage of approximately 1.2 V. When SS/ENA

exceeds the enable threshold, device start-up begins. The

reference voltage fed to the error amplifier is linearly

ramped up from 0 V to 0.891 V in 3.35 ms. Similarly, the

converter

output

voltage

reaches

regulation

in

approximately 3.35 ms. Voltage hysteresis and a 2.5-

µs

falling edge deglitch circuit reduce the likelihood of

triggering the enable due to noise.