TPS54873

SLVS444 – OCTOBER 2002

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high-side FET off and the low-side FET on. The device

operates at its maximum duty cycle until the output voltage

rises to the regulation set-point, setting VSENSE to

approximately the same voltage as VREF. If the error

amplifier output is low, the PWM latch is continually reset

and the high-side FET does not turn on. The low-side FET

remains on until the VSENSE voltage decreases to a

range that allows the PWM comparator to change states.

The TPS54873 is capable of sinking current continuously

until the output reaches the regulation set-point.

If the current limit comparator trips for longer than 100 ns,

the PWM latch resets before the PWM ramp exceeds the

error amplifier output. The high-side FET turns off and

low-side FET turns on to decrease the energy in the output

inductor and consequently the output current. This

process is repeated each cycle in which the current limit

comparator is tripped.

DEAD-TIME CONTROL AND MOSFET

DRIVERS

Adaptive dead-time control prevents shoot-through

current from flowing in both N-channel power MOSFETs

during the switching transitions by actively controlling the

turnon times of the MOSFET drivers. The high-side driver

does not turn on until the voltage at the gate of the low-side

FET is below 2 V. While the low-side driver does not turn

on until the voltage at the gate of the high-side MOSFET

is below 2 V.

The high-side and low-side drivers are designed with

300-mA source and sink capability to quickly drive the

power MOSFETs gates. The low-side driver is supplied

from VIN, while the high-side drive is supplied from the

BOOT pin. A bootstrap circuit uses an external BOOT

capacitor and an internal 2.5-

Ω bootstrap switch

connected between the VIN and BOOT pins. The

integrated bootstrap switch improves drive efficiency and

reduces external component count.

OVERCURRENT PROTECTION

The cycle-by-cycle current limiting is achieved by sensing

the current flowing through the high-side MOSFET and

comparing this signal to a preset overcurrent threshold.

The high side MOSFET is turned off within 200 ns of

reaching the current limit threshold. A 100-ns leading edge

blanking circuit prevents current limit false tripping.

Current limit detection occurs only when current flows from

VIN to PH when sourcing current to the output filter. Load

protection during current sink operation is provided by

thermal shutdown.

THERMAL SHUTDOWN

The device uses the thermal shutdown to turn off the power

MOSFETs and disable the controller if the junction

temperature exceeds 150

°C. The device is released from

shutdown automatically when the junction temperature

decreases to 10

°C below the thermal shutdown trip point,

and starts up under control of the slow-start circuit.

Thermal shutdown provides protection when an overload

condition is sustained for several milliseconds. With a

persistent fault condition, the device cycles continuously;

starting up by control of the soft-start circuit, heating up due

to the fault condition, and then shutting down upon

reaching the thermal shutdown trip point. This sequence

repeats until the fault condition is removed.

POWER-GOOD (PWRGD)

The power good circuit monitors for under voltage

conditions on VSENSE. If the voltage on VSENSE is 10%

below the reference voltage, the open-drain PWRGD

output is pulled low. PWRGD is also pulled low if VIN is

less than the UVLO threshold or SS/ENA is low, or a

thermal shutdown occurs. When VIN

≥ UVLO threshold,

SS/ENA

the open drain output of the PWRGD pin is high. A

edge deglitch circuit prevent tripping of the power good

comparator due to high frequency noise.