TPS54873

SLVS444 – OCTOBER 2002

www.ti.com

12

The second function of the SS/ENA pin provides an

external means of extending the slow-start time with a

low-value capacitor connected between SS/ENA and

AGND.

Adding a capacitor to the SS/ENA pin has two effects on

start-up. First, a delay occurs between release of the

SS/ENA pin and start-up of the output. The delay is

proportional to the slow-start capacitor value and lasts

until the SS/ENA pin reaches the enable threshold. The

start-up delay is approximately:

t

d +

C

(SS)

1.2 V

5

mA

Second, as the output becomes active, a brief ramp-up at

the internal slow-start rate may be observed before the

externally set slow-start rate takes control and the output

rises at a rate proportional to the slow-start capacitor. The

slow-start time set by the capacitor is approximately:

t

(SS) +

C

(SS)

0.7 V

5

mA

The actual slow-start time is likely to be less than the above

approximation due to the brief ramp-up at the internal rate.

The low side MOSFET is off during the slow-start

sequence.

VBIAS REGULATOR (VBIAS)

The VBIAS regulator provides internal analog and digital

blocks with a stable supply voltage over variations in

junction temperature and input voltage. A high quality,

low-ESR, ceramic bypass capacitor is required on the

VBIAS

pin.

X7R

or

X5R

grade

dielectrics

are

recommended because their values are more stable over

temperature. The bypass capacitor must be placed close

to the VBIAS pin and returned to AGND.

External loading on VBIAS is allowed, with the caution that

internal circuits require a minimum VBIAS of 2.70 V, and

external loads on VBIAS with ac or digital switching noise

may degrade performance. The VBIAS pin may be useful

as a reference voltage for external circuits.

VOLTAGE REFERENCE

signal by scaling the output of a temperature stable

bandgap circuit. During manufacture, the bandgap and

scaling circuits are trimmed to produce 0.891 V at the

output of the error amplifier, with the amplifier connected

as a voltage follower. The trim procedure adds to the high

precision regulation of the TPS54873, since it cancels

offset errors in the scale and error amplifier circuits.

OSCILLATOR AND PWM RAMP

The oscillator frequency can be set to internally fixed

values of 350 kHz or 550 kHz using the SYNC pin as a

static digital input. If a different frequency of operation is

required for the application, the oscillator frequency can be

externally adjusted from 280 to 700 kHz by connecting a

resistor between the RT pin and AGND and floating the

SYNC pin. The switching frequency is approximated by

the following equation, where R is the resistance from RT

to AGND:

Switching Frequency

+ 100 kW

R

500 [kHz]

External synchronization of the PWM ramp is possible

over the frequency range of 330 kHz to 700 kHz by driving

a synchronization signal into SYNC and connecting a

resistor from RT to AGND. Choose a resistor between the

RT and AGND which sets the free running frequency to

80% of the synchronization signal. The following table

summarizes the frequency selection configurations:

SWITCHING

FREQUENCY

SYNC PIN

RT PIN

350 kHz, internally set

Float or AGND

Float

550 kHz, internally set

≥ 2.5 V

Float

Externally set 280 kHz

to 700 kHz

Float

R = 180 k

Ω to 68 kΩ

Externally

synchronized

frequency

Synchronization

signal

R = RT value for 80%

of external synchro-

nization frequency

ERROR AMPLIFIER

The high performance, wide bandwidth, voltage error

amplifier sets the TPS54873 apart from most dc/dc

converters. The user is given the flexibility to use a wide

range of output L and C filter components to suit the

particular

application

needs.

Type

2

or

type

3

compensation

can

be

employed

using

external

compensation components.

PWM CONTROL

Signals from the error amplifier output, oscillator, and

current limit circuit are processed by the PWM control

logic. Referring to the internal block diagram, the control

logic includes the PWM comparator, OR gate, PWM latch,

and portions of the adaptive dead-time and control logic

block. During steady-state operation below the current

limit threshold, the PWM comparator output and oscillator

pulse train alternately reset and set the PWM latch. Once

the PWM latch is reset, the low-side FET remains on for a

minimum duration set by the oscillator pulse width. During

this period, the PWM ramp discharges rapidly to its valley

voltage. When the ramp begins to charge back up, the

low-side FET turns off and high-side FET turns on. As the

PWM ramp voltage exceeds the error amplifier output

voltage, the PWM comparator resets the latch, thus

turning off the high-side FET and turning on the low-side

FET. The low-side FET remains on until the next oscillator

pulse discharges the PWM ramp.

During transient conditions, the error amplifier output

could be below the PWM ramp valley voltage or above the

PWM peak voltage. If the error amplifier is high, the PWM

latch is never reset, and the high-side FET remains on until

the oscillator pulse signals the control logic to turn the

(2)

(3)

(4)