MB96310 datasheet(7/82 Pages) CYPRESS

7 / 82 page

Document Number: 002-04592 Rev. *A

Page 6 of 81

MB96310 Series

2. Block Diagram

Block diagram of MB96(F)31x

DMA

Controller

Boot ROM

Peripheral

Bus Bridge

Peripheral

Bus Bridge

16FX Core Bus (CLKB)

USART

3 ch.

10-bit ADC

12 ch.

I/O Timer 0

ICU 0/1

CAN

Interface

1 ch.

Real Time

Clock

Watchdog

RAM

Voltage

Regulator

SIN2, SIN2_R, SIN7_R, SIN8_R

SOT2, SOT2_R, SOT7_R, SOT8_R

SCK2, SCK2_R, SCK7_R, SCK8_R

IN0, IN1

OUT6, OUT7

TX2

RX2

VCC

VSS

I/O Timer 1

ICU 4/5/6

IN4, IN5

16FX

CPU

Interrupt

Controller

Clock &

Mode Controller

Flash

Memory A

Memory Patch

Unit

NMI

OCU 6/7

16-bit Reload

Timer

4 ch.

TIN1

TOT0_R, TOT2_R

TOT1, TOT3

External

Interrupt

INT0, INT8 ... INT13

INT2_R, INT4_R

INT3_R1

INT7_R, INT10_R

16-bit PPG

14 ch.

PPG0, PPG1, PPG3, PPG4

TTG0, TTG1, TTG4, TTG8, TTG9, TTG12

PPG8_R, PPG9_R, PPG16_R ... PPG19_R

TTG8_R, TTG9_R, TTG16_R, TTG17_R

CKOT0_R, CKOT1, CKOT1_R

CKOTX1

X0, X1

X0A, X1A *1

RSTX

MD0...MD2

RLT6

*1: X0A, X1A only available on devices with suffix “W”

I/O Timer 2

ICU 9

I/O Timer 3

ICU 10

AVCC

AVSS

AVRH

AN0, AN1, AN3, AN4

ADTG_R

AN6 ... AN10

AN12, AN14, AN16

PPG6, PPG7, PPG12, PPG14

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