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MB96310 数据表(PDF) 2 Page - Cypress Semiconductor

部件名 MB96310
功能描述  F2MC-16FX 16-bit Proprietary Microcontroller
PDF  82 Pages
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制造商  CYPRESS [Cypress Semiconductor]
网页  http://www.cypress.com
标志 CYPRESS - Cypress Semiconductor

MB96310 数据表(HTML) 2 Page - Cypress Semiconductor

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MB96310 Series
F2MC-16FX 16-bit Proprietary
Microcontroller
Cypress Semiconductor Corporation
198 Champion Court
San Jose
, CA 95134-1709
408-943-2600
Document Number: 002-04592 Rev. *A
Revised April 22, 2016
MB96310 series is based on Cypress advanced 16FX architecture (16-bit with instruction pipeline for RISC-like performance). The
CPU uses the same instruction set as the established 16LX series - thus allowing for easy migration of 16LX Software to the new
16FX products. 16FX improvements compared to the previous generation include significantly improved performance - even at the
same operation frequency, reduced power consumption and faster start-up time.
For highest processing speed at optimized power consumption an internal PLL can be selected to supply the CPU with up to 56MHz
operation frequency from an external 4MHz resonator. The result is a minimum instruction cycle time of 17.8ns going together with
excellent EMI behavior. An on-chip clock modulation circuit significantly reduces emission peaks in the frequency spectrum. The
emitted power is minimized by the on-chip voltage regulator that reduces the internal CPU voltage. A flexible clock tree allows to select
suitable operation frequencies for peripheral resources independent of the CPU speed.
Features
Technology
0.18m CMOS
CPU
F2MC-16FX CPU
Up to 56 MHz internal, 17.8 ns instruction cycle time
Optimized instruction set for controller applications (bit, byte,
word and long-word data types; 23 different addressing modes;
barrel shift; variety of pointers)
8-byte instruction execution queue
Signed multiply (16-bit ×16-bit) and divide (32-bit/16-bit)
instructions available
System clock
On-chip PLL clock multiplier (x1 - x25, x1 when PLL stop)
3 MHz - 16 MHz external crystal oscillator clock (maximum
frequency when using ceramic resonator depends on
Q-factor).
Up to 56 MHz external clock
32-100 kHz subsystem quartz clock
100kHz/2MHz internal RC clock for quick and safe startup,
oscillator stop detection, watchdog
Clock source selectable from main- and subclock oscillator
(part number suffix “W”) and on-chip RC oscillator, indepen-
dently for CPU and 2 clock domains of peripherals.
Low Power Consumption - 13 operating modes : (different Run,
Sleep, Timer modes, Stop mode)
Clock modulator
On-chip voltage regulator
Internal voltage regulator supports reduced internal MCU
voltage, offering low EMI and low power consumption figures
Low voltage reset
Reset is generated when supply voltage is below minimum.
Code Security
Protects ROM content from unintended read-out
Memory Patch Function
Replaces ROM content
Can also be used to implement embedded debug support
DMA
Automatic transfer function independent of CPU, can be
assigned freely to resources
Interrupts
Fast Interrupt processing
8 programmable priority levels
Non-Maskable Interrupt (NMI)
Timers
Three independent clock timers (23-bit RC clock timer, 23-bit
Main clock timer, 17-bit Sub clock timer)
Watchdog Timer
CAN
Supports CAN protocol version 2.0 part A and B
ISO16845 certified
Bit rates up to 1 Mbit/s
32 message objects
Each message object has its own identifier mask
Programmable FIFO mode (concatenation of message
objects)
Maskable interrupt
Disabled Automatic Retransmission mode for Time Triggered
CAN applications
Programmable loop-back mode for self-test operation



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