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MB91F525FHDPMC 数据表(PDF) 139 Page - Cypress Semiconductor |
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MB91F525FHDPMC 数据表(HTML) 139 Page - Cypress Semiconductor |
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139 / 280 page  Document Number: 002-04662 Rev. *F Page 139 of 280 MB91520 Series Parameter Symbol Pin Name Conditions Value Unit Remarks Min Typ Max “H” level input voltage VIH1 P000,002,003, 005,020,022, 024,026,150, 151,035,041, 045,055,057, 071-077,081, 082,093,096, 097,100-102, 111,115,116, 122,126,130, 134,142,143, 144,153 CMOS hysteresis input level 0.7× VCC - VCC V VIH3 Port other than VIH1 Automotive input level 0.8× VCC - VCC V VIH5 RSTX,NMIX,MD 0,MD1 CMOS hysteresis input level 0.8× VCC - VCC V VIHT DEBUGIF TTL input level 2 - VCC V “L” level input voltage VIL1 P000,002,003, 005,020,022, 024,026,150, 151,035,041, 045,055,057, 071-077,081, 082,093,096, 097,100-102, 111,115,116, 122,126,130, 134,142,143, 144,153 CMOS hysteresis input level Vss - 0.3× VCC V VIL3 Port other than VIH1 Automotive input level Vss - 0.5× VCC V VIL5 RSTX,NMIX,MD 0,MD1 CMOS hysteresis input level Vss - 0.2× VCC V VILT DEBUGIF TTL input level Vss - 0.8 V *: It is a standard in BRAMSC (Backup RAM sleep control bit) = 1 (Enter the state of the sleep at the standby mode) condition. |
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