MB91F525FHDPMC datasheet(159/280 Pages) CYPRESS

159 / 280 page

Document Number: 002-04662 Rev. *F

Page 159 of 280

MB91520 Series

Parameter

Symbol

Pin Name

Conditions

Value

Unit

Remarks

Min

Max

SCS↓→SCK↓

setup time

tCSSE

SCK1 to SCK11

SCS1 to SCS3,

SCS40 to SCS43,

SCS50 to SCS53,

SCS60 to SCS63,

SCS70 to SCS73,

SCS8 to SCS11

3tCPP+30

External shift

clock mode

output pin:

CL = 50 pF

SCK↑→SCS↑

hold time

tCSHE

SCS

deselect time

tCSDE

SCS1 to SCS3,

SCS40 to SCS43,

SCS50 to SCS53,

SCS60 to SCS63,

SCS70 to SCS73,

SCS8 to SCS11

3tCPP+30

SCS↓→SOT

delay time

tDSE

SCS1 , SCS2,

SCS50 to SCS53,

SCS60 to SCS63,

SCS70 to SCS73,

SCS8 to SCS11

SOT1 , SOT2 ,

SOT5 to SOT11

SCS3,

SCS40 to SCS43

SOT3 , SOT4

300

SCS↑→SOT

delay time

tDEE

SCS1 to SCS3,

SCS40 to SCS43,

SCS50 to SCS53,

SCS60 to SCS63,

SCS70 to SCS73,

SCS8 to SCS11

SOT1 to SOT11

External shift

clock mode

output pin:

CL = 50 pF

SCK↓→SCS↓

clock

switch

time

tSCC

SCK1 , SCK2,

SCK5 to SCK11

SCS1 , SCS2,

SCS50 to SCS53,

SCS60 to SCS63,

SCS70 to SCS73,

SCS8 to SCS11

3tCPP-10

3tCPP+50

Internal shift

clock mode

Round operation

output pin:

CL = 50 pF

SCK3 , SCK4

SCS3 ,

SCS40 to SCS43

3tCPP-300

3tCPP+50

*1: tCSSU = SCSTR:CSSU7-0×Serial chip select timing operating clock

*2: tCSHD = SCSTR:CSHD7-0×Serial chip select timing operating clock

*3: tCSDS = SCSTR:CSDS15-0×Serial chip select timing operating clock

Regardless of the deselect time setting, once after the serial chip select pin becomes inactive, it will take

at least five peripheral bus clock cycles to be active again

Please see the hardware manual for details of above-mentioned *1,*2, and *3.

MB91F525FHDPMC 数据表(PDF) 159 Page - Cypress Semiconductor

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