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MB91F525FHDPMC 数据表(PDF) 162 Page - Cypress Semiconductor |
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MB91F525FHDPMC 数据表(HTML) 162 Page - Cypress Semiconductor |
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162 / 280 page  Document Number: 002-04662 Rev. *F Page 162 of 280 MB91520 Series (4-1-6) Bit setting: SMR:MD2 = 0, SMR:MD1 = 1, SMR:MD0 = 0, When Serial chip select is used : SCSCR:CSEN = 1, Serial clock output mark level "L" : SMR,SCSFR:SCINV = 1, Serial chip select Inactive level "H" : SCSCR,SCSFR:CSLVL = 1 (TA:-40 °C to +125 °C, VCC = AVCC = 5.0 V ± 10 %/VCC = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0.0V) Parameter Symbol Pin Name Conditions Value Unit Remarks Min Max SCS↓→SCK↑ setup time tCSSI SCK1 , SCK2, SCK5 to SCK11 SCS1 , SCS2, SCS50 to SCS53, SCS60 to SCS63, SCS70 to SCS73, SCS8 to SCS11 - tCSSU-50 *1 tCSSU+0 *1 ns Internal shift clock mode output pin : CL = 50 pF SCK3 , SCK4 SCS3 , SCS40 to SCS43 tCSSU-50 *1 tCSSU+300 *1 ns SCK↓→SCS↑ hold time tCSHI SCK1 , SCK2, SCK5 to SCK11 SCS1 , SCS2, SCS50 to SCS53, SCS60 to SCS63, SCS70 to SCS73, SCS8 to SCS11 tCSHD-10 *2 tCSHD+50 *2 ns SCK3 , SCK4 SCS3 , SCS40 to SCS43 tCSHD-300 *2 tCSHD+50 *2 ns SCS deselect time tCSDI SCS1 to SCS3, SCS40 to SCS43, SCS50 to SCS53, SCS60 to SCS63, SCS70 to SCS73, SCS8 to SCS11 tCSDS-50 *3 tCSDS+50 *3 ns |
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