MB91F525FHDPMC datasheet(176/280 Pages) CYPRESS

176 / 280 page

Document Number: 002-04662 Rev. *F

Page 176 of 280

MB91520 Series

(4-4) I2C timing

(TA: -40 °C to +125 °C, VCC = AVCC = 5.0 V ± 10 %/VCC = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0.0 V)

Parameter

Symbol

Pin Name

Conditions

Standard Mode

Fast Mode*3

Unit

Remarks

Min

Max

Min

Max

SCL clock frequency

fSCL

SCK3 to

SCK11

CL = 50 pF

R = (VP/IOL) *1

100

400

kHz

Repeat "start" condition

hold time

SDA ↓ → SCL ↓

tHDSTA

SOT3 to

SOT11,

(SDA)

SCK3 to

SCK11,

(SCL)

4.0

–

0.6

–

μs

Period of "L" for SCL

clock

tLOW

SCK3 to

SCK11,

(SCL)

4.7

–

1.3

–

μs

Period of "H" for SCL

clock

tHIGH

SCK3 to

SCK11,

(SCL)

4.0

–

0.6

–

μs

Repeat "start" condition

setup time

SCL ↑ → SDA ↓

tSUSTA

SCK3 to

SCK11,

(SCL)

4.7

–

0.6

–

μs

Data hold time

SCL ↓ → SDA ↓ ↑

tHDDAT

SOT3 to

SOT11,

(SDA)

SCK3 to

SCK11,

(SCL)

3.45*2

0.9*3

μs

Data setup time

SDA ↓ ↑ → SCL ↑

tSUDAT

SOT3 to

SOT11,

(SDA)

SCK3 to

SCK11,

(SCL)

250

–

100

–

"Stop" condition setup

time

SCL ↑ → SDA ↑

tSUSTO

SOT3 to

SOT11,

(SDA)

SCK3 to

SCK11,

(SCL)

4.0

–

0.6

–

μs

Bus-free time between

"stop" condition and

"start" condition

tBUF

–

4.7

–

1.3

–

μs

Noise filter

tSP

–

2tCPP*4

–

2tCPP*4

–

Notes: Only ch.3 and ch.4 are standard mode/fast mode correspondence. In ch.5-ch.8, ch.10, and ch.11, only a standard mode is

correspondences.

*1: R and CL represent the pull-up resistance and load capacitance of the SCL and SDA output lines,

respectively.

Vp shows that the power-supply voltage of the pull-up resistor and IOL shows the VOL guarantee current.

*2: The maximum tHDDAT only has to be met if the device does not extend the "L" width (tLOW) of the SCL signal.

*3: A fast mode I2C bus device can be used on a standard mode I2C bus system as long as the device satisfies the requirement of

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