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MB91F525FHDPMC 数据表(PDF) 180 Page - Cypress Semiconductor |
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MB91F525FHDPMC 数据表(HTML) 180 Page - Cypress Semiconductor |
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180 / 280 page  Document Number: 002-04662 Rev. *F Page 180 of 280 MB91520 Series (9) Low voltage detection (Internal low-voltage detection) (TA: -40 °C to +125 °C, VSS = AVSS = 0.0 V) Parameter Symbol Pin Name Conditions Value Unit Remarks Min Typ Max Power supply voltage range VRDP5 - - 0.6 - 1.4 V Detection voltage*2 VRDL *1 0.8 0.9 1.0 V When power-supply voltage falls Hysteresis width VRHYS - - 0.1 - V When power-supply voltage rises Low voltage detection time - - - - 30 µs *1: If the fluctuation of the power supply is faster than the low voltage detection time, there is a possibility to generate or release after the power supply voltage has exceeded the detection voltage range. *2: The detection voltage of the internal low voltage detection is 0.9 V ± 0.1 V. This LVD cannot be used to reliably generate a reset before voltage dips below minimum guaranteed MCU operation voltage, as this detection level is below the minimum guaranteed MCU operation voltage. Below the minimum guaranteed MCU operation voltage, MCU operations are not guaranteed with the exception of LVD. (10) External bus I/F (synchronous mode) timing (TA: -40 °C to +105 °C, VCC = AVCC = 5.0 V ± 10 %/VCC = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0.0 V) (external load capacitance 50 pF) Parameter Symbol Pin Name Value Unit Remarks Min Max Cycle time tCYC SYSCLK 25 - ns VCC = 5.0 V ± 10 %*1 31.25 VCC = 3.3 V ± 0.3 V ASX delay time tCHASL, tCHASH SYSCLK ASX 0.5 18 ns CS0X to CS3X delay time tCHCSL, tCHCSH SYSCLK CS0X to CS3X 0.5 18 ns A00 to A21 delay time tCHAV, tCHAX SYSCLK A00 to A21 0.5 18 ns RDX delay time tCHRL, tCHRH SYSCLK RDX 0.5 18 ns RDX minimum pulse tRLRH RDX tCYC× 2 - 20 - ns RWT = 1, set RWT to 1 or more.*2 Data setup → RDX↑time tDSRH RDX D16 to D31 18+tCYC - ns Same as above RDX↑→ data hold tRHDH 0 - ns |
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