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MB91F525FHDPMC 数据表(PDF) 181 Page - Cypress Semiconductor |
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MB91F525FHDPMC 数据表(HTML) 181 Page - Cypress Semiconductor |
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181 / 280 page  Document Number: 002-04662 Rev. *F Page 181 of 280 MB91520 Series Parameter Symbol Pin Name Value Unit Remarks Min Max WRnX delay time tCHWL, tCHWH SYSCLK WR0X, WR1X 0.5 18 ns WRnX minimum pulse tWLWH WR0X, WR1X tCYC - 10 - ns WWT = 0 *2 SYSCLK↑→ data output time tCHDV SYSCLK D16 to D31 0.5 18 ns SYSCLK↑→ data hold time tCHDX - 18 ns Set WRCS to 1 or more. SYSCLK↑→ address output time tCHMAV SYSCLK D16 to D31 0.5 18 ns SYSCLK↑→ address hold time tCHMAX - 18 ns In multiplex mode, set as follows: Set CSWR and CSRD to 2 or more. ASCY must satisfy the following conditions because of setting ADCY > ASCY and protocol violation prevention. ADCY +1 ≤ ACS + CSRD ADCY +1 ≤ ACS + CSWR ASCY + 1 ≤ ACS + CSRD ASCY + 1 ≤ ACS + CSWR See Hardware Manual for details. *1: Please use it with external load capacity 12 pF or less for VCC = 3.3 V ± 0.3 V (40 MHz operation). *2: If the bus is expanded by automatic wait insertion or RDY input, add time (tCYC × the number of expanded cycles) to the rated value. |
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