STA003T datasheet(9/32 Pages) STMICROELECTRONICS

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3 - I

2C BUS SPECIFICATION

The STA003T supports the I

2C protocol. This pro-

tocol defines any device that sends data on to the

bus as a transmitter and any device that reads

the data as a receiver. The device that controls

the data transfer is known as the master and the

others as the slave. The master always starts the

transfer and provides the serial clock for synchro-

nisation. The STA003T is always a slave device

in all its communications.

3. 1 - COMMUNICATION PROTOCOL

3.1.0 - Data transition or change

Data changes on the SDA line must only occur

when the SCL clock is low. SDA transition while

the clock is high are used to identify START or

STOP condition.

3.1.1 - Start condition

START is identified by a high to low transition of

the data bus SDA signal while the clock signal

SCL is stable in the high state. A START condi-

tion must precede any command for data transfer.

3.1.2 - Stop condition

STOP is identified by low to high transition of the

data bus SDA signal while the clock signal SCL is

stable in the high state. A STOP condition termi-

nates communications between STA003T and

the bus master.

3.1.3 - Acknowledge bit

An acknowledge bit is used to indicate a success-

ful data transfer. The bus transmitter, either mas-

ter or slave, releases the SDA bus after sending

8 bit of data.

During the 9th clock pulse the receiver pulls the

SDA bus low to acknowledge the receipt of 8 bits

of data.

3.1.4 - Data input

During the data input the STA003T samples the

SDA signal on the rising edge of the clock SCL.

For correct device operation the SDA signal has

to be stable during the rising edge of the clock

and the data can change only when the SCL line

is low.

3.2 - DEVICE ADDRESSING

To start communication between the master and

the STA003T, the master must initiate with a start

condition. Following this, the master sends onto

the SDA line 8 bits (MSB first) corresponding to

the device select address and read or write

mode.

The 7 most significant bits are the device address

identifier, corresponding to the I

2C bus definition.

For the STA003T these are fixed as 1000011.

The 8th bit (LSB) is the read or write operation

RW, this bit is set to 1 in read mode and 0 for

write

mode.

After

START

condition

the

STA003T identifies on the bus the device ad-

dress and, if a match is found, it acknowledges

the identification on SDA bus during the 9th bit

time. The following byte after the device identifi-

cation byte is the internal space address.

3.3 - WRITE OPERATION (see fig. 9)

Following a START condition the master sends a

device select code with the RW bit set to 0.

The STA003T acknowledges this and waits for

the byte of internal address.

After receiving the internal bytes address the

STA003T again responds with an acknowledge.

3.3.1 - Byte write

In the byte write mode the master sends one data

byte, this is acknowledged by STA003T. The

master then terminates the transfer by generating

a STOP condition.

3.3.2 - Multibyte write

The multibyte write mode can start from any inter-

nal address.

The transfer is terminated by the

master generating a STOP condition.

DEV-ADDR

ACK

START

D98AU825B

SUB-ADDR

ACK

DATA IN

ACK

STOP

BYTE

WRITE

DEV-ADDR

ACK

START

SUB-ADDR

ACK

DATA IN

ACK

STOP

MULTIBYTE

WRITE

DATA IN

ACK

Figure 9. Write Mode Sequence

STA003T

9/32

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