100nF

1

2

100nF

14

13

100nF

16

15

100nF

23

22

17

18

27

28

26

RESET

24

TESTEN

25

SCANEN

VDD_5/CLK_OUT

100nF

4.7

µF

4.7

µF

10K

1K

4.7nF

470pF

19

20

21

8

7

6

5

12

11

10

9

4

3

XTO

XTI

SCR_INT

BIT_EN

SCKR

SDI

OCLK

LRCKT

SCKT

SDO

SCL

SDA

D99AU1004

Figure 3. Test Circuit

OUTPUT

D98AU967

Test Load Circuit

Output

SDA

1mA

100pF

3.6V

Other Outputs

100

µA100µA

100pF

1.5V

Test Load

2. FUNCTIONAL DESCRIPTION

2.1 - Clock Signal

The STA003T input clock is derivated from an ex-

ternal source or from a 14.72 MHz crystal.

XTI is an input Pad with specific levels.

Symbol

Parameter

Test Condition

Min.

Typ.

Max.

Unit

Low Level Input Voltage

V

High Level Input Voltage

V

CMOS compatibility

The XTI pad low and high levels are CMOS compatible; XTI pad noise margin is better than typical

CMOS pads.

TTL compatibility

3V TTL min high level = 2.0V while XTI min high level = 2.2V)

STA003T

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