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STA003T 数据表(PDF) 29 Page - STMicroelectronics |
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STA003T 数据表(HTML) 29 Page - STMicroelectronics |
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29 / 32 page ![]() SCKR(SCLK_POL=2) SDI SCKR(SCLK_POL=0) t_biten tsdi_hold tsdi_setup D98AU971 tsckr_min_hi tlo BIT_EN t_biten tsckr_min_hi tsckr_min_period 5.4.2. Bitstream input interface (SDI, SCKR, BIT_EN) tsdi_setup_min = 2ns tsdi_hold_min = 3ns tsckr_min_hi = 10ns tsckr_min_low = 10ns tsckr_min_lperiod = 50ns t_biten (min) = 2ns SRC_INT D98AU972 t_src_hi t_src_low 5.4.3. SRC_INT This is an asynchronous input used in "broadcast’ mode. SRC_INT is active low t_src_low min duration is 50ns (1DSP clock period) t_src_high min duration is 50ns (1DSP clock period) XTI (INPUT) XTO CLK_OUT txto tclk_out D98AU973 thi tlo 5.4.4. XTI,XTO and CLK_OUT timings txto = 1.40 + pad_timing (Cload_XTO) ns RESET D98AU974 treset_low_min 5.4.5. RESET The Reset min duration (t_reset_low_min) is 100ns STA003T 29/32 |
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