STA003T datasheet(21/32 Pages) STMICROELECTRONICS

21 / 32 page

PCMCROSS

Address: 0x56

Type: R/W

Software Reset: 0x00

Hardware Reset: 0x00

MSB

LSB

Description

Left channel is mapped on the left output.

Right channel is mapped on the Right output

Left channel is duplicated on both Output channels.

Right channel is duplicated on both Output channels

Right and Left channels are toggled

The default configuration for this register is ’0x00’.

ANCILLARY DATA BUFFER

Address: 0x59 - 0x5D

Type: RO

Software Reset: 0x00

Hardware Reset: 0x00

STA003T can extract max 56 bytes/MPEG frame.

To know the number of A.D. bits available every

MPEG frame, the ANCCOUNT_L and ANC-

COUNT_H registers (0x41 and 0x42) have to be

read.

The buffer dimension is 5 bytes, written by

STA003T core in sequential order. The timing in-

formation to read the buffer can be obtained by

reading the FRAME_CNT registers (0x67 - 0x69).

To fill up the buffer with a new 5-bytes slot, the

STA003T waits until a CMD_INTERRUPT regis-

ter is written by the master.

MFSDF (X)

Address: 0x61

Type: R/W

Software Reset: 0x0F

Hardware Reset: 0x0F

MSB

LSB

M3M2M1M0

The register contains the values for PLL X divider

(see Fig. 6).

The value is changed by the internal STA003T

Core, to set the clock frequencies, according to

the incoming bitstream. This value can be even

set by the user to select the PCM interface con-

figuration.

The VCO output frequency is divided by (X+1).

DAC_CLK_MODE

Address: 0x63

Type: RW

Software Reset: 0x00

Hardware Reset: 0x00

MSB

LSB

XXXXXXX

MODE

This register is used to select the operating mode

for OCLK clock signal.

If it is set to ’1’, the OCLK frequency is fixed, and

it is mantained to the value fixed by the user even

if the sampling frequency of the incoming bit-

stream changes.

If the MODE flag is set to ’0’, the OCLK frequency

changes, and can be set to (512, 384, 256) * Fs.

The default configuration for this mode is 256 *

Fs.

When this mode is selected, the default OCLK

frequency is 12.288 MHz.

STA003T

21/32

STA003T 数据表(PDF) 21 Page - STMicroelectronics

STA003T 数据表(HTML) 21 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

数据表下载

链接网址

STA003T 数据表(PDF) 21 Page - STMicroelectronics

STA003T 数据表(HTML) 21 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

数据表 下载

链接网址

数据表下载