CS5345

2

TABLE OF CONTENTS

1. PIN DESCRIPTIONS ............................................................................................................... 3

2. CHARACTERISTICS AND SPECIFICATIONS ....................................................................... 5

SPECIFIED OPERATING CONDITIONS ................................................................................. 5

ABSOLUTE MAXIMUM RATINGS ........................................................................................... 5

ADC ANALOG CHARACTERISTICS ....................................................................................... 6

ADC ANALOG CHARACTERISTICS ....................................................................................... 8

ADC DIGITAL FILTER CHARACTERISTICS ........................................................................... 9

PGAOUT ANALOG CHARACTERISTICS.............................................................................. 10

PGAOUT ANALOG CHARACTERISTICS (CONT’D)............................................................. 11

PGAOUT ANALOG CHARACTERISTICS (CONT’D)............................................................. 12

DC ELECTRICAL CHARACTERISTICS................................................................................. 13

DIGITAL INTERFACE CHARACTERISTICS.......................................................................... 14

SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT ................................................. 15

SWITCHING CHARACTERISTICS - CONTROL PORT - I²C FORMAT ................................ 18

SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT ............................... 19

3. TYPICAL CONNECTION DIAGRAM ..................................................................................... 20

4. APPLICATIONS ..................................................................................................................... 21

4.1 Recommended Power-Up Sequence ............................................................................. 21

4.2 System Clocking ............................................................................................................. 21

4.2.1 Master Clock ...................................................................................................... 21

4.2.2 Master Mode ...................................................................................................... 22

4.2.3 Slave Mode ........................................................................................................ 22

4.3 High Pass Filter and DC Offset Calibration ..................................................................... 22

4.4 Analog Input Multiplexer, PGA, and Mic Gain ................................................................. 23

4.5 Input Connections ........................................................................................................... 23

4.6 PGA Auxiliary Analog Output .......................................................................................... 23

4.7 Control Port Description and Timing ............................................................................... 24

4.7.1 SPI Mode ........................................................................................................... 24

4.7.2 I²C Mode ............................................................................................................ 25

4.8 Interrupts and Overflow ...................................................................................................27

4.9 Reset ............................................................................................................................. 27

4.10 Synchronization of Multiple Devices ............................................................................. 27

4.11 Grounding and Power Supply Decoupling .................................................................... 27

5. REGISTER QUICK REFERENCE ......................................................................................... 28

6. REGISTER DESCRIPTION ................................................................................................... 29

6.1 Chip ID - Register 01h ....................................................................................................29

6.2 Power Control - Address 02h .......................................................................................... 29

6.3 ADC Control - Address 04h ............................................................................................ 29

6.4 MCLK Frequency - Address 05h ..................................................................................... 30

6.5 PGAOut Control - Address 06h ....................................................................................... 31

6.6 Channel A PGA Control - Address 07h ........................................................................... 31

6.7 Channel B PGA Control - Address 08h ........................................................................... 31

6.8 ADC Input Control - Address 09h ................................................................................... 32

6.9 Active Level Control - Address 0Ch ................................................................................ 33

6.10 Interrupt Status - Address 0Dh ..................................................................................... 33

6.11 Interrupt Mask - Address 0Eh ....................................................................................... 34

6.12 Interrupt Mode MSB - Address 0Fh .............................................................................. 34

6.13 Interrupt Mode LSB - Address 10h ............................................................................... 34

7. PARAMETER DEFINITIONS ................................................................................................. 35

8. PACKAGE DIMENSIONS ...................................................................................................... 36

9. THERMAL CHARACTERISTICS AND SPECIFICATIONS ................................................. 36

Appendix A: Filter Plots

....................................................................................................... 37