CS5345

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4. APPLICATIONS

4.1

Recommended Power-Up Sequence

1)

Hold RESET low until the power supply, MCLK, and LRCK are stable. In this state, the Control Port is reset to

its default settings.

2)

Bring RESET high. The device will remain in a low power state with the PDN bit set by default. The control port

will be accessible.

3)

The desired register settings can be loaded while the PDN bit remains set.

4)

Clear the PDN bit to initiate the power-up sequence.

4.2

System Clocking

The CS5345 will operate at sampling frequencies from 4 kHz to 200 kHz. This range is divided into three speed

modes as shown in Table 1 below.

4.2.1

Master Clock

MCLK/LRCK must maintain an integer ratio as shown in Table 2. The LRCK frequency is equal to Fs, the frequency

at which audio samples for each channel are clocked out of the device. The FM bits (see page 30) and the MCLK

Freq bits (see page 30) configure the device to generate the proper clocks in Master Mode and receive the proper

clocks in Slave Mode. Table 2 illustrates several standard audio sample rates and the required MCLK and LRCK

frequencies.

Mode

Sampling Frequency

Single Speed

4-50 kHz

Double Speed

50-100 kHz

Quad Speed

100-200 kHz

Table 1. Speed Modes