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CS5345 数据表(PDF) 32 Page - Cirrus Logic

部件名 CS5345
功能描述  105 DB 24BIT 192 KHZ STEREO AUDIO ADC
PDF  39 Pages
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制造商  CIRRUS [Cirrus Logic]
网页  http://www.cirrus.com
标志 CIRRUS - Cirrus Logic

CS5345 数据表(HTML) 32 Page - Cirrus Logic

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CS5345
32
example settings.
6.8
ADC Input Control - Address 09h
6.8.1
PGA Soft Ramp or Zero Cross Enable (Bits 4:3)
Function:
Soft Ramp Enable
Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally
ramping, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock
periods. See Table 10 on page 33.
Zero Cross Enable
Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will
occur on a signal zero crossing to minimize audible artifacts. The requested level change will occur
after a time-out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample
rate) if the signal does not encounter a zero crossing. The zero cross function is independently mon-
itored and implemented for each channel. See Table 10 on page 33.
Soft Ramp and Zero Cross Enable
Soft Ramp and Zero Cross Enable dictate that signal level changes, either by attenuation changes or
muting, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level
change will occur after a time-out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms
at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is
independently monitored and implemented for each channel. See Table 10 on page 33.
Table 9. Example Gain and Attenuation Settings
Gain[5:0]
Setting
101000
-12 dB
000000
0 dB
011000
+12 dB
76543
210
Reserved
Reserved
Reserved
PGASoft
PGAZero
Sel2
Sel1
Sel0



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