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TUSB1002AI 数据表(PDF) 23 Page - Texas Instruments

部件名 TUSB1002AI
功能描述  USB3.2 10 Gbps Dual-Channel Linear Redriver
PDF  31 Pages
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

TUSB1002AI 数据表(HTML) 23 Page - Texas Instruments

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SATA
Device
12nF (max)
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SATA
Express
Device
176nF t 265nF
+
-
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PCIe
Device
75nF t 265nF
23
TUSB1002A
www.ti.com
SLLSF63 – MARCH 2018
Product Folder Links: TUSB1002A
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
SATA device is present. The ferrite bead chosen must present at least 600 ohms impedance at 100MHz so as to
not impact high-speed signalling. It is recommended to use Murata BLM03AG601SN1 or BLM03HD601SN1D or
a ferrite bead with similar characteristics from a different vendor. For applications which only require support for
PCIe and SATA Express and do not need to support SATA, the ferrite beads and 49.9 ohm resistors are not
needed.
Figure 21. AC-Coupling capacitor Implementation for SATA, SATA Express, and PCIe Devices
The TUSB1002A power is at P(U0_SSP_1200mV) when both its upstream and downstream paths are enabled. In
order to save system power in system S3/S4/S5 states, it is suggested to control the TUSB1002A EN pin.
Anytime the system enters a low power state (S3, S4, or S5), it is suggested to de-assert the EN pin. While EN
pin is de-asserted, the TUSB1002A will consume P(SHUTDOWN). Assertion of this pin is necessary anytime the
system exits a lower power state.
The TUSB1002A compensates for channel loss in both the upstream (C to D) and downstream direction (A to B).
This is done by configuring the CH1_EQ[2:1] and CH2_EQ[2:1] pins to the equalization setting that matches as
close possible to the channel insertion loss. In this particular example, CH2_EQ[2:1] is for path A to B which is
the channel between PCIe/SATA/SATA Express host and the TUSB1002A, and CH1_EQ[2:1] is for path C to D
which is the channel between TUSB1002A and the miniCard/mSATA socket.
In this particular example, the channel A-B has a trace length of 8 inches with a 4 mil trace width. This particular
channel has about 0.83 dB per inch of insertion loss at 5 GHz. This equates to approximately 6.7 dB of loss for
the entire 8 inches of trace as depicted in Figure 19. An additional 1.5 dB of loss is added due to package of the
PCIe/SATA/SATA Express Host, TUSB1002A, and the A/C coupling capacitor. This brings the entire channel
loss at 5 GHz to 6.7 dB + 1.5 dB = 8.2 dB. The channel A-B for this example is connected to TUSB1002A
RX2P/N input and therefore CH2_EQ[2:1] pins are used for adjusting TUSB1002A RX2P/N equalization settings.
The CH2_EQ[2:1] pins should be set such that TUSB1002A equalization is between 5dB and 8dB. A value closer
to 5 dB maybe best if Host has transmitter de-emphasis.
A similar method should be used for the upstream path (C to D). In this particular example, C to D has a trace
length of 2 inches with a 4-mil trace width. This equates to approximately 1.5 dB at 5 GHz. The SATA/SATA
Express/PCIe device will have its own channel loss. This loss can be added to the C to D channel loss. For this
example, we will assume a value of 5dB is acceptable to compensate for C to D channel loss as well as loss
associated with the SATA/SATA Express/PCIe device. The CH1_EQ[2:1] pins should be set such that
TUSB1002A equalization is 5dB.



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