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TUSB1002A

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SLLSF63 – MARCH 2018

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Copyright © 2018, Texas Instruments Incorporated

8.3.3 Application Curves

Figure 23. PCIe Gen1 TX Eye Diagram

Figure 24. PCIe Gen 3 TX Eye Diagram

9 Power Supply Recommendations

near the TUSB1002A.

10 Layout

10.1 Layout Guidelines

•

RXP/N and TXP/N pairs should be routed with controlled 90-Ω differential impedance (±15%).

•

Keep away from other high speed signals.

•

In USB3 applications maintaining polarity thru the TUSB1002A is not necessary. Therefore it is recommended

to connect polarity in such a way that produces the best routing.

•

Intra-pair routing should be kept to within 2 mils.

•

Intra-pair length matching should be near the location of mismatch.

•

Inter-pair length matching is not necessary.

•

Each pair should be separated at least by 3 times the signal trace width.

•

The use of bends in differential traces should be kept to a minimum. When bends are used, the number of left

and right bends should be as equal as possible and the angle of the bend should be

≥ 135 degrees. This

minimizes any length mismatch causes by the bends; ad therefore, minimize the impact bends have on EMI.

•

Route all differential pairs on the same of layer.

•

The number of VIAS should be kept to a minimum. It is recommended to keep the VIAS count to 2 or less.

•

Keep traces on layers adjacent to ground plane.

•

Do NOT route differential pairs over any plane split.

•

When using thru-hole USB connectors, it is recommend to route differential pairs on bottom layer in order to

minimize the stub created by the thru-hole connector.

•

Adding Test points causes impedance discontinuity; and therefore, negatively impact signal performance. If

test points are used, they should be placed in series and symmetrically. They must not be placed in a manner

that causes a stub on the differential pair.