LTP5901-IPR datasheet(21/34 Pages) LINER

21 / 34 page

LTP5901-IPR/LTP5902-IPR

59012iprfa

For more information www.linear.com/LTP5901-IPR or www.linear.com/LTP5902-IPR

pin FuncTions

VSUPPLY: System and I/O Power Supply. Provides power

to the module. The digital-interface I/O voltages are also

set by this voltage.

ANTENNA: Multiplexed Receiver Input and Transmitter

Output Pin. The impedance presented to the MMCX con-

nectorshouldbe50Ω,single-endedwithrespecttoground.

RESETn:Theasynchronousresetsignalisinternallypulled

up. Resetting Eterna will result in the ARM Cortex-M3

rebooting and loss of network connectivity. Use of this

signal for resetting Eterna is not recommended, except

during power-on and in-circuit programming.

RADIO_INHIBIT: The radio inhibit function is currently

not supported by software. RADIO_INHIBIT provides a

mechanism for an external device to temporarily disable

radiooperation.Failuretoobservethetimingrequirements

defined in the RADIO_INHIBIT AC Characteristics section,

may result in unreliable netowrk operation. In designs

where the RADIO_INHIBIT function is not needed the

input must either be tied, pulled or actively driven low to

avoid excess leakage.

TMS, TCK, TDI, TDO: JTAG port supporting software

debug and boundary scan.

SLEEPn: The SLEEPn function is not currently supported

in software. The SLEEPn input must either be tied, pulled

or actively driven high to avoid excess leakage.

UART_RX,UART_RX_RTSn,UART_RX_CTSn,UART_TX,

UART_TX_RTSn,UART_TX_CTSn:TheAPIUARTinterface

includes bi-directional wake up and flow control. Unused

inputsignalsmustbedrivenorpulledtotheirinactivestate.

TIMEn:StrobingtheTIMEninputisthemostaccuratemeth-

odtoacquirethenetworktimemaintainedbyEterna.Eterna

latches the network timestamp with sub-microsecond

resolution on the rising edge of the TIMEn signal and

produces a packet on the API serial port containing the

timing information.

UARTC0_RX, UARTC0_TX, UARTC1_RX, UARTC1_TX:

The CLI UART provides a mechanism for monitoring,

configuration and control of Eterna during operation. On

the LTP5901/2-IPR CLI UART 0 is used when Eterna is not

configured to support external RAM and CLI UART 1 is

used when Eterna is configured to support external RAM.

For a complete description of the supported commands

see the SmartMesh IP Manager CLI Guide.

EB_DATA_0 through EB_DATA_7, EB_ADDR_0, EB_

ADDR_1, EB_IO_LE1 through EB_IO_LE2, EB_IO_CS0n,

EB_IO_WEn, EB_IO_ENn: The external bus provides a

multiplexed address data bus enabling the Cortex-M3

direct access of external byte wide RAM. The additional

RAM is used by network management software enabling

thesupportofalargernetworkofmoteswithhigherpacket

throughput. To support the addressing needed, each

latch signal, EB_IO_LE0, EB_IO_LE1, and EB_IO_LE2 will

strobe to latch 8-bits of address from the EB_DATA[7:0]

bus.EB_IO_LE0,EB_IO_LE1,andEB_IO_LE2correspond

to addres bits [25:18], [17:10] and [9:2] respectively.

EB_ADDR_0 and EB_ADDR_1 correspond to the lower

two bits of address. For systems with 256k bytes or less

EB_IO_LE2canbeignored.EB_IO_CS0n,EB_IO_WEnand

EB_IO_OEn provide chip select, write enable and output

enable control of the external RAM.

FLASH_P_ENn, IPCS_SSn, IPCS_SCK, IPCS_MISO,

IPCS_SSn: The In-circuit programming control system

(IPCS)busenablesin-circuitprogrammingofEterna’sflash

memory. IPCS_SCK is a clock and should be terminated

appropriately for the driving source to prevent overshoot

and ringing.

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