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ISL8117DEMO2Z 数据表(PDF) 16 Page - Renesas Technology Corp

部件名 ISL8117DEMO2Z
功能描述  Synchronous Step-Down PWM Controller
PDF  24 Pages
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制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

ISL8117DEMO2Z 数据表(HTML) 16 Page - Renesas Technology Corp

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ISL8117
FN8666 Rev 4.00
Page 16 of 24
Apr 19, 2018
Gate Driver
The low-side gate driver is supplied from VCC5V and provides a 2A
peak sink and source current. The high-side gate driver is also
capable of delivering the same currents as the low-side gate driver.
Gate-drive voltage for the upper N-channel MOSFET is generated
by a flying capacitor boot circuit. A boot capacitor connected from
the BOOT pin to the PHASE node provides power to the high-side
MOSFET driver. To limit the peak current in the IC, an external
resistor can be placed between the BOOT pin and the boot
capacitor. This small series resistor also damps any oscillations
caused by the resonant tank of the parasitic inductances in the
traces of the board and the FET’s input capacitance.
At start-up, the low-side MOSFET turns on first and forces PHASE
to ground in order to charge the BOOT capacitor to 5V. After the
low-side MOSFET turns off, the high-side MOSFET is turned on by
closing an internal switch between BOOT and UGATE. This
provides the necessary gate-to-source voltage to turn on the
upper MOSFET, an action that boosts the 5V gate drive signal
above VIN. The current required to drive the upper MOSFET is
drawn from the internal 5V regulator.
For optimal EMI performance or reducing phase node ringing, a
small resistor might be placed between the BOOT pin to the
positive terminal of the bootstrap capacitor.
Adaptive Dead Time
The ISL8117 incorporates an adaptive dead time algorithm on
the synchronous buck PWM controller that optimizes operation
with varying MOSFET conditions. This algorithm provides
approximately 16ns dead time between the switching of the
upper and lower MOSFETs. This dead time is adaptive and allows
operation with different MOSFETs without having to externally
adjust the dead time using a resistor or capacitor. During turn-off
of the lower MOSFET, the LGATE voltage is monitored until it
reaches a threshold of 1V, at which time the UGATE is released to
rise. Adaptive dead time circuitry monitors the upper MOSFET
gate voltage during UGATE turn-off. Once the upper MOSFET
gate-to-source voltage has dropped below a threshold of 1V, the
LGATE is allowed to rise. It is recommended to not use a resistor
between UGATE and LGATE and the respective MOSFET gates as
it may interfere with the dead time circuitry.
Internal Bootstrap Diode
The ISL8117 has an integrated bootstrap diode to help reduce
total cost and reduce layout complexity. Simply adding an
external capacitor across the BOOT and PHASE pins completes
the bootstrap circuit. The bootstrap capacitor can be chosen from
Equation 6.
where QGATE is the amount of gate charge required to fully
charge the gate of the upper MOSFET. The
VBOOT term is defined
as the allowable droop in the rail of the upper drive.
As an example, suppose an upper MOSFET has a gate charge
(QGATE) of 25nC at 5V and also assume the droop in the drive
voltage over a PWM cycle is 200mV. Based on the calculation, a
bootstrap capacitance of at least 0.125µF is required. The next
larger standard value capacitance of 0.22µF should be used. A
good quality ceramic capacitor is recommended.
The internal bootstrap Schottky diode has a resistance of 1.5Ω
(typical) at 800mA. Combined with the resistance RBOOT, this
could lead to the boot capacitor charging insufficiently in cases
where the bottom MOSFET is turned on for a very short period of
time. If such circumstances are expected, an additional external
Schottky diode may be added from VCC5V to the positive of the
boot capacitor. RBOOT may still be necessary to lower EMI due to
fast turn-on of the upper MOSFET.
Power-Good Indicator
The power-good pin can be used to monitor the status of the
output voltage. PGOOD will be true (open drain) 1.1ms after the
FB pin is within ±11% of the reference voltage.
There is no extra delay when the PGOOD pin is pulled LOW.
Protection Circuits
The converter output is monitored and protected against
overload, light-load, and undervoltage conditions.
Undervoltage Lockout
The ISL8117 includes UVLO protection, which keeps the device in
a reset condition until a proper operating voltage is applied. It
also shuts down the ISL8117 if the operating voltage drops below
a predefined value. The controller is disabled when UVLO is
asserted. When UVLO is asserted, PGOOD is valid and will be
deasserted.
BOOT
UGATE
PHASE
VCC_5V
VIN
ISL8117
FIGURE 31. UPPER GATE DRIVER CIRCUIT
CB
RBOOT
OPTIONAL
EXTERNAL
SCHOTTKY
BOOT
QGATE
V
BOOT
------------------------
(EQ. 6)



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