CS5014 datasheet(21/40 Pages) CIRRUS

21 / 40 page

obtain the specified accuracy. Figure 11 illustrates

this operation. During pre-charge the charge on

the capacitor array first settles to the buffered ver-

sion of the analog input. This voltage is offset

from the actual input voltage. During fine-charge,

the charge then settles to the accurate unbuffered

version.

The acquisition time of the CS5012A/14/16 de-

pends on the CLKIN frequency. This is due to a

fixed pre-charge period. For instance, operating

the CS5012A, CS5014, or CS5016 -16

version with an external 4 MHz CLKIN results in

a 3.75

µs acquisition time: 1.5 µs for pre-charging

(6 clock cycles) and 2.25

µs for fine-charging.

Fine-charge settling is specified as a maximum of

2.25

µs for an analog source impedance of less

than 200

Ω. (For the CS5012A -7 version it is

specified as 1.32

µs.) In addition, the comparator

requires a source impedance of less than 400

Ω

around 2 MHz for stability, which is met by prac-

tically all bipolar op amps. Large dc source

impedances can be accommodated by adding ca-

pacitance from AIN to ground (typically 200 pF)

to decrease source impedance at high frequencies.

However, high dc source resistances will increase

the input’s RC time constant and extend the nec-

essary acquisition time. For more information on

input applications, consult the application note:

Input Buffer Amplifiers for the CS501X Family of

A/D Converters.

During the first six clock cycles following a con-

version (pre-charge) in unipolar mode, the

CS5012A is capable of slewing at 20V/

µs and the

CS5014/16 can slew at 5V/

µs. In bipolar mode,

only half the capacitor array is connected to the

analog input so the CS5012A can slew at 40V/

µs,

and the CS5014/16 can slew at 10V/

µs. After the

first six CLKIN cycles, the CS5012A will slew at

1.25V/

µs in unipolar mode and 3.0V/µs in bipolar

mode, and the CS5014/16 will slew at 0.25V/

µs

in unipolar mode and 0.5V/

µs in bipolar mode.

Acquisition of fast slewing signals (step func-

tions) can be hastened if the step occurs during or

immediately following the conversion cycle. For

instance, channel selection in multiplexed appli-

cations should occur while the CS5012A/14/16 is

converting (see Figure 12). Multiplexer settling is

thereby removed from the overall throughput

equation, and the CS5012A/14/16 can convert at

full speed.

Convert Channel N+1

Convert Channel N

Address N

Address N + 1

Address N + 2

Address N + 3

EOC

Output

HOLD

Input

MUX

Address

MUX Settling

to Channel N + 2

Analog

Input

MUX Settling

to Channel N + 1

CS5012A/14/16

Figure 12. Pipelined MUX Input Channels

CS5012A, CS5014, CS5016

DS14F8

2-27

CS5012A CS5014 CS5016

DS14F9

CS5014 数据表(PDF) 21 Page - Cirrus Logic

CS5014 数据表(HTML) 21 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

数据表下载