CS5014 datasheet(29/40 Pages) CIRRUS

29 / 40 page

are therefore used to remove frequency compo-

nents in the input signal which are above one-half

the sample rate. However, all wideband noise in-

troduced by the CS5016 still aliases into the

baseband. This "white" noise is evenly spread

from dc to one-half the sampling rate and inte-

grates to 35

µV rms in unipolar mode.

Noise can be reduced by sampling at higher than

the desired word rate and averaging multiple

samples for each word. Oversampling spreads the

CS5016’s noise over a wider band (for lower

noise density), and averaging applies a low-pass

response which filters noise above the desired

signal bandwidth. In general, the CS5016’s noise

performance can be maximized in any application

by always sampling at the maximum specified

rate of 50 kHz (for lowest noise density) and

digitally filtering to the desired signal bandwidth.

CS5014 and CS5016 Sampling Distortion

The ultimate limitation on the CS5014/16’s

linearity (and distortion) arises from nonideal

sampling of the analog input voltage. The cali-

brated capacitor array used during conversions is

also used to track and hold the analog input sig-

nal. The conversion is not performed on the

analog input voltage per se, but is actually per-

formed on the charge trapped on the capacitor ar-

ray at the moment the HOLD command is given.

The charge on the array is ideally related to the

analog input voltage by Qin = -Vin x Ctot as

shown in Figure 2. Any deviation from this ideal

relationship will result in conversion errors even

if the conversion process proceeds flawlessly.

At dc, the DAC capacitor array’s voltage coeffi-

cient dictates the converter’s linearity. This

variation in capacitance with respect to applied

signal voltage yields a nonlinear relationship be-

tween charge Qin and the analog input voltage

Vin and places a bow or wave in the transfer

function. This is the dominant source of distor-

tion at low input frequencies (Figures 21 and 23).

The ideal relationship between Qin and Vin can

also be distorted at high signal frequencies due to

nonlinearities in the internal MOS switches. Dy-

namic signals cause ac current to flow through

the switches connecting the capacitor array to the

analog input pin in the track mode. Nonlinear on-

resistance in the switches causes a nonlinear

voltage drop. This effect worsens with increased

signal frequency as shown in Figures 25 and 27

since the magnitude of the steady state current in-

creases. First noticeable at 1 kHz, this distortion

assumes a linear relationship with input fre-

quency. With signals 20 dB or more below

full-scale, it no longer dominates the converter’s

overall S/(N+D) performance (Figures 30-33).

This distortion is strictly an ac sampling phe-

nomenon. If significant energy exists at high

frequencies, the effect can be eliminated using an

external track-and-hold amplifier to allow the ar-

ray’s charge current to decay, thereby eliminating

any voltage drop across the switches. Since the

CS5014/16 has a second sampling function on-

chip, the external track-and-hold can return to the

track mode once the converter’s HOLD input

falls. It need only acquire the analog input by the

time the entire conversion cycle finishes.

Code (Hexadecimal)

Counts:

911

3470

599

80CB

80CC

80CD

80CF

80D0

80CE

80CA

1000

2000

3000

4000

5000

Count

Noiseless

CS5016

Converter

Figure

29. Histogram Plot of 5000 Conversion

Inputs from the CS5016

CS5012A, CS5014, CS5016

DS14F8

2-35

CS5012A CS5014 CS5016

DS14F9

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