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IMX7SCEC 数据表(PDF) 104 Page - NXP Semiconductors |
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IMX7SCEC 数据表(HTML) 104 Page - NXP Semiconductors |
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104 / 152 page  Electrical characteristics i.MX 7Solo Family of Applications Processors Datasheet, Rev. 5, 07/2017 NXP Semiconductors 104 Figure 77. SAI timing — master modes S5 SAI_BCLK to SAI_FS output valid — 15 ns S6 SAI_BCLK to SAI_FS output invalid 0 — ns S7 SAI_BCLK to SAI_TXD valid — 15 ns S8 SAI_BCLK to SAI_TXD invalid 0 — ns S9 SAI_RXD/SAI_FS input setup before SAI_BCLK 15 — ns S10 SAI_RXD/SAI_FS input hold after SAI_BCLK 0 — ns Table 79. Master mode SAI timing Num Characteristic Min Max Unit S11 SAI_BCLK cycle time (input) 40 — ns S12 SAI_BCLK pulse width high/low (input) 40% 60% BCLK period S13 SAI_FS input setup before SAI_BCLK 10 — ns S14 SAI_FA input hold after SAI_BCLK 2 — ns S15 SAI_BCLK to SAI_TXD/SAI_FS output valid — 20 ns S16 SAI_BCLK to SAI_TXD/SAI_FS output invalid 0 — ns S17 SAI_RXD setup before SAI_BCLK 10 — ns S18 SAI_RXD hold after SAI_BCLK 2 — ns Table 78. Master mode SAI timing(continued) Num Characteristic Min Max Unit |
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