AD8330

Data Sheet

Rev. H | Page 4 of 32

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

LINEAR GAIN INTERFACE

Pin VMAG, Pin CMGN

See the Circuit Description section

3.8

4.0

4.2

V/V

×2

Usable Input Range

0

5

V

Default Voltage

0.48

0.5

0.52

V

Incremental Resistance

4

kΩ

Bandwidth

150

MHz

CHIP ENABLE

Pin ENBL

Logic Voltage for Full Shutdown

0.5

V

Logic Voltage for Hibernate Mode

Output pins remain at CNTR

1.3

1.5

1.7

V

Logic Voltage for Full Operation

2.3

V

Current in Full Shutdown

20

100

µA

Current in Hibernate Mode

1.5

mA

1.7

µs

POWER SUPPLY

VPSI, VPOS, VPSO, COMM, and CMOP pins

Supply Voltage

2.7

6

V

Quiescent Current

20

27

mA

1

The use of an input common-mode voltage significantly different from the internally set value is not recommended due to its effect on noise performance. See Figure 56.

2

See the Typical Performance Characteristics section for more detailed information on distortion in a variety of operating conditions.

3

For minimum sized coupling capacitors.