AD8330 datasheet(23/32 Pages) AD

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Data Sheet

AD8330

Rev. H | Page 23 of 32

FREQUENCY (Hz)

50k

–10

10M

OFST: ENABLED

DISABLED

VDBS = 1.5V

VDBS = 0.75V

VDBS = 0V

Figure 59. Input CMRR vs. Frequency for Various Values of VDBS

FREQUENCY (Hz)

–600

–20

–30

–10

–400

–300

–200

–100

LINE 1

LINE 3

LINE 4

LINE 2

LINE 4

LINE 1

LINE 3

LINE 2

10M

100M

500M

–500

Figure 60. AC Gain and Phase for Various Loading Conditions

When driving a single-sided load, either OPHI or OPLO can be

used. These outputs are very symmetric, so the only effect of

this choice is to select the desired polarity. However, when the

frequency range of interest extends to the upper limits of the

AD8330, attach a dummy resistor of the same value to the

unused output. Figure 60 illustrates the ac gain and phase

response for various loads and VDBS = 0.75 V. Line 1 shows the

unloaded (CL = 12 pF) case for reference; the gain is 6 dB lower

(20 dB) using only the single-sided output. Adding a 75 Ω load

from OPHI to an ac ground results in Line 2. The gain becomes

a factor of ×1.5 V or 3.54 dB lower, but artifacts of the output

common-mode control loop appear in both the magnitude and

phase response.

Adding a dummy 75 Ω to OPLO results in Line 3: the gain is a

further 2.5 dB lower, at about 14 dB. The CM artifacts are no longer

present but a small amount of peaking occurs. If objectionable, this

can be eliminated by raising both of the capacitors on the

output pins to 25 pF, as shown in Line 4 of Figure 60.

The gain reduction incurred both by using only one output and

by the additional effect of loading can be overcome by taking

advantage of the VMAG feature, provided primarily for just such

circumstances. Thus, to restore the basic gain in the first case

(Line 1), apply a 1 V source to this pin; to restore the gain in the

second case, this voltage must be raised by a factor of ×1.5 to 1.5 V.

In Case 3 and Case 4, a further factor of ×1.33 is needed to make

up the 2.5 dB loss, that is, raise VMAG to 2 V. With the restoration

of gain, the peak output swing at the load is, likewise restored to

±2 V.

Pulse Operation

When using the AD8330 in applications where its transient

response is of greater interest and the outputs are conveyed to

their loads via coaxial cables, the added capacitances can slightly

differ in value, and can be placed either at the sending or load

end of the cables, or divided between these nodes. Figure 61

shows an illustrative example where dual, 1 meter, 75 Ω cables

are driven through dc-blocking capacitors and are independently

terminated at ground level.

Because of the considerable variation between applications, only

general recommendations can be made with regard to minimizing

pulse overshoot and droop. The former can be optimized by

adding small load capacitances, if necessary; the latter requires

the use of sufficiently large capacitors (C1).

Figure 62 shows typical results for VDBS = 0.24 V, a square wave

input amplitude of 450 mV (the actual combination is not

important), a rise time of 2 ns, and VMAG raised to 2.0 V. In the

upper waveforms, the load capacitors are both zero, and a small

amount of overshoot is visible; with 40 pF, the response is cleaner.

A shunt capacitance of 20 pF from OPHI to OPLO has a similar

effect. Coupling capacitors for this demonstration are sufficiently

large to prevent any visible droop over this time scale. The outputs

at the load side eventually assume a mean value of zero, with

negative and positive excursions depending on the duty cycle.

COMM

OPHI

INLO

OPLO

INHI

VPSI

VPSO

CMOP

MODE

VDBS

CMGN

VMAG

OFST

VPOS

BIAS AND

V-REF

GAIN INTERFACE

CM MODE AND

OFFSET CONTROL

OUTPUT

STAGES

OUTPUT

CONTROL

VGA CORE

CD2

CD3

RD2

VS 2.7V–6V

CL1

CL2

RL1

RL2

Figure 61. Driving Dual Cables with Grounded Loads

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