AD8330 datasheet(21/32 Pages) AD

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Data Sheet

AD8330

Rev. H | Page 21 of 32

Thus, when RL = 150 Ω, the gain is reduced by 6 dB; for RL = 75 Ω,

the reduction is 9.5 dB; and for RL = 50 Ω, it is 12 dB.

Gain Errors Due to On-Chip Resistor Tolerances

In all cases where external resistors are used, keep in mind that

all on-chip resistances, including the RO and the input resistance

(RI), are subject to variances of up to ±20%.

These variances need to be accounted for when calculating the

gain with input and output loading. This sensitivity can be avoided

by adjusting the source and load resistances to bear an inverse

relationship as follows:

If RS = αRI, then make RL = RO/α; or,

if RL = αRO, then make RS = RI/α

The simplest case is when RS = 1 kΩ and RL = 150 Ω, therefore,

the gain is 12 dB lower than the basic value. The reduction of

peak swing at the load can be corrected by using VMAG = 1 V,

thereby restoring 6 dB of gain; using VMAG = 2 V restores the full

basic gain and doubles the peak available output swing.

Output (Input) Common-Mode Control

The output voltages are nominally positioned at the midpoint of

the supply, VS/2, over the range 2.7 V < VS < 6 V, and this voltage

appears at Pin CNTR, which is not normally expected to be loaded

(the source resistance is ~4 kΩ). However, some circumstances

require a small change in this voltage, and a resistor from CNTR to

ground can lower this voltage, whereas a resistor to the supply

raises it. On the other hand, this pin can be driven by an external

voltage source to set the common-mode level to satisfy, for

example, the needs of a following ADC. Any value from 0.5 V

above ground to 0.5 V below the supply is permissible. Of course,

when using an extreme common-mode level, the available

output swing is limited, and it is recommended that a value equal

or close to the default of VCNTR = VS/2 be used. There may be a

few millivolts of offset between the applied voltage and the

actual common-mode level at the output pins.

The input common-mode voltage, VCMI, at Pin INHI and

Pin INLO is slaved to the output. It bears a y = mx + b linear

and offset relationship to VCNTR as shown in Equation 14 where

y = VCMI, m = 0.757, x = VCNTR, and b = 1.12 V for VDBS = 0.75 V

and T = 25°C.

VCMI = 0.757 VCNTR + 1.12 V

(14)

The effects of VDBS and ambient temperature on VCMI are shown

in Figure 55. Thus, the default value for VCMI for VDBS = 0.75V,

T = 25°C and VS = 5 V is 3.01 V.

USING THE AD8330

This section describes a few general aspects of using the AD8330.

Applying the AD8330 to a wide variety of circumstances requires

very few precautions.

As in all high frequency circuits, careful observation of the ground

nodes associated with each function is important. Three positive

supply pins are provided: VPSI supports the input circuitry that

often operates at a relatively high sensitivity; VPOS supports

general bias sources and needs no decoupling; and VPSO biases

the output stage where decoupling can be useful in maintaining

a glitch-free output. Figure 57 shows the general case, where VPSI

and VPSO are each provided with their own decoupling network,

but this is not needed in all cases.

COMM

OPHI

INLO

OPLO

INHI

VPSI

VPSO

CMOP

MODE

VDBS

CMGN

VMAG

OFST

VPOS

BIAS AND

V-REF

GAIN INTERFACE

CM MODE AND

OFFSET CONTROL

OUTPUT

STAGES

OUTPUT

CONTROL

VGA CORE

OUTPUT,

±2V MAX

BASIC GAIN BIAS

VDBS: 0V TO 1.5V

CD2

CD1

CD3

RD2

GROUND

VS 2.7V TO 6V

INPUT,

0V TO ±2V MAX

Figure 57. Power Supply Decoupling and Basic Connections

Because of the differential nature of the signal path, power

supply decoupling is, in general, much less critical than in a

single-sided amplifier; and where the minimization of board-

level components is especially crucial, it is possible that these

pins need no decoupling at all. On the other hand, when the

signal source is single-sided, giving extra attention to the

decoupling on Pin VPSI is sometimes required. Likewise, care is

required in decoupling the VPSO pin if the output is loaded on

only one of its two output pins. The general common (COMM)

and the output stage common (CMOP) are usually grounded as

shown in the Figure 57; however, the Applications Information

section shows how a negative supply can optionally be used.

The AD8330 is enabled by taking the ENBL pin to a logical high

(or, in all cases, the supply). The UP gain mode is enabled either

by leaving the MODE pin unconnected or taking it to a logical

high. When the opposite gain direction is needed, ground the

MODE pin or drive it to a logical low. The CHPF capacitor

determines the low-pass corner of the offset loop; this is

preferably tied to the CNTR pin that in turn, must be decoupled

to ground. The gain interface common pin (CMGN) is

grounded, and the output magnitude control pin (VMAG) is

left unconnected, or can optionally be connected to a 500 mV

source for basic gain calibration.

Connections to the input and output pins are not shown in Figure 57

because of the many options that are available. When the AD8330 is

used to drive an ADC, connect the OPHI and OPLO pins directly

to the differential inputs of a suitable converter, such as an AD9214.

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