AD8124

Data Sheet

Rev. A | Page 14 of 15

A suitable filter that uses a surface-mount ferrite bead is shown

in Figure 27, and its frequency response is shown in Figure 28.

Because the frequency response was taken using a 50 Ω network

analyzer and with only one 0.1 μF capacitor on the AD8124 side,

the actual amount of rejection provided by the filter in a real-world

application is different from that shown in Figure 28. The general

shape of the rejection curve, however, matches Figure 28, providing

substantially increased overall PSRR from approximately 5 MHz to

500 MHz, where it is most needed. One filter is required on each

of the two supplies (not one filter per supply pin).

FAIR-RITE

2743021447

*ALL AD8124 SUPPLY PINS ARE INDIVIDUALLY

DECOUPLED WITH A 0.1µF CAPACITOR.

0.1µF

4700pF

4700pF

SYSTEM

SUPPLY

TO AD8124*

Figure 27. Power Supply Filter

–120

–100

–80

–60

–40

–20

0

10k

100k

1M

10M

100M

FREQUENCY (Hz)

Figure 28. Power Supply Filter Frequency Response in a 50 Ω System

LAYOUT AND POWER SUPPLY DECOUPLING

CONSIDERATIONS

Standard high speed PCB layout practices should be adhered

to when designing with the AD8124. A solid ground plane is

required and controlled impedance traces should be used when

interconnecting the high speed signals. Source termination resistors

on all outputs must be placed as close as possible to the output pins.

The exposed paddle on the underside of the AD8124 must be

connected to a pad that connects to at least one PCB plane.

Several thermal vias should be used to make the connection

between the pad and the plane(s).

High quality 0.1 μF power supply decoupling capacitors should

be placed as close as possible to all supply pins. Small surface-

mount ceramic capacitors should be used, and tantalum capacitors

are recommended for bulk supply decoupling.

POWER-DOWN

The power-down feature is intended to be used to reduce power

consumption when a particular device is not in use and does

not place the output in a high-Z state when asserted. The input

logic levels and supply current in power-down mode are presented

in the Power Supply section of Table 1.