AD8134ACPZ-R2 datasheet(14/20 Pages) AD

14 / 20 page

AD8134

Data Sheet

Rev. B | Page 14 of 20

CALCULATING AN APPLICATION CIRCUIT’S INPUT

IMPEDANCE

The effective input impedance of a circuit such as that in

Figure 30 at VIP and VIN depends on whether the amplifier is

being driven by a single-ended or differential signal source. For

balanced differential input signals, the differential input

impedance, RIN, dm, between the inputs VIP and VIN is simply

RIN,dm = 2 × RG = 1.5 kΩ

In the case of a single-ended input signal (for example, if VIN is

grounded and the input signal is applied to VIP), the input

impedance becomes

(

)

125













−

The circuit’s input impedance is effectively higher than it would

be for a conventional op amp connected as an inverter because

a fraction of the differential output voltage appears at the inputs

as a common-mode signal, partially bootstrapping the voltage

across the input resistor RG.

INPUT COMMON-MODE VOLTAGE RANGE IN

SINGLE-SUPPLY APPLICATIONS

The inputs of the AD8134 are designed to facilitate level-

shifting of ground referenced input signals on a single power

supply. For a single-ended input, this would imply, for example,

that the voltage at VIN in Figure 30 would be 0 V when the

amplifier’s negative power supply voltage was also set to 0 V.

It is important to ensure that the common-mode voltage at the

amplifier inputs, VAP and VAN, stays within its specified range.

Since voltages VAP and VAN are driven to be essentially equal by

negative feedback, the amplifier’s input common-mode voltage

can be expressed as a single term, VACM. VACM can be calculated as

2 ICM

OCM

ACM

where VICM is the common-mode voltage of the input signal,

that is,

ICM

DRIVING A CAPACITIVE LOAD

A purely capacitive load can react with the output impedance

of the AD8134 to reduce phase margin, resulting in high

frequency ringing in the pulse response. The best way to

minimize this effect is to place a small resistor in series with

each of the amplifier’s outputs to buffer the load capacitance.

OUTPUT PULL-DOWN (OPD)

The AD8134 has an OPD pin that when pulled high

significantly reduces the power consumed while simultaneously

pulling the outputs to within less than 1 V of VS− when used

with series diodes (see the Applications section). The equivalent

schematic of the output in the output pull-down state is shown

in Figure 31. (The ESD diodes shown in Figure 31 are for ESD

protection and are distinct from the series diodes used with the

output pull-down feature.) See Figure 18 and Figure 24 for the

output pull-down transient and isolation performance. The

threshold levels for the OPD input pin are referenced to the

positive power supply and are listed in the Specifications tables.

When the OPD pin is pulled high, the AD8134 enters the

output pull-down state.

VOUT

VCC

PULL-DOWN

(OUTPUT IS

PULLED DOWN

WHEN SWITCH

IS CLOSED)

VS–

VS+

ESD DIODE

Figure 31. Output Pull-Down Equivalent Circuit

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