ADL5240ACPZ-R7 datasheet(17/28 Pages) AD

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Data Sheet

ADL5240

Rev. A | Page 17 of 28

Amplifier Bias

The dc bias for the amplifier in ADL5240 is supplied through

Inductor L1 and is connected to the AMPOUT pin. Three

decoupling capacitors (C3, C4, and C5)are used to prevent

RF signals from propagating onto the dclines. The dcsupply

ranges from 4.75 V to 5.25 V and should be connected to the

VCC test point on the evaluation board.

Digital Step Attenuator Bias

The bias for the DSA is provided through the VDDpin. At least

one decoupling capacitor (C8)is recommendedon the VDD

trace. The voltage ranges from4.75 V to 5.25 V and should be

connected to the VDD test point on theevaluationboard. The

DSA is shown to workfor dcvoltages as low as 2.5 V.

Amplifier RF Input Interface

Pin 15 is the RF input for the amplifier of ADL5240. The

amplifier is internally matched to 50 Ω at the input; therefore,

no external componentsare required. Only a dcblocking

capacitor (C1)is required.

Amplifier RF Output Interface

Pin 10 is the RF output for the amplifier ofADL5240. The

amplifier is internally matched to 50 Ω at the output; therefore,

no external componentsare required. Only a dcblocking

capacitor (C2)is required. The bias is provided through this pin

via a choke inductor.

DSA RF Input Interface

Pin 4 is the RF input for the DSA of ADL5240. The input

impedance of the DSA is close to 50 Ω over the entire frequency

range; therefore, no external components arerequired. Only a

dc blocking capacitor (C6)is required.

DSA RF Output Interface

Pin 21 is the RF output for the DSA ofADL5240. The output

impedance of the DSA is close to 50 Ω over the entire frequency

range; therefore, no external components arerequired. Only a

dc blocking capacitor (C7)is required.

DSA SPI Interface

The DSA of the ADL5240 can operate in either serial or parallel

mode.Pin 32 (SEL)controlsthemodeof operation. Toselect serial

mode, connect SEL to ground; to select parallel mode, connect

SEL to VDD. In parallel mode, Pin 25 to Pin 30 (D6 to D1) are

the data bits, with D6 being the LSB. Connect Pin 31 (D0) to

ground during the parallel modeof operation. In serial mode,

Pin 29 is the latch enable (LE), Pin 30 is the data (DATA), and

Pin 31 is the clock(CLK). Pin 26, Pin 27, and Pin 28 are not used

in serial mode and should be connectedto ground. Pin 25 (D6)

should beconnectedto VDDduring theserial mode of operation.

To preventnoisefromcoupling onto thedigital signals, anRC filter

can be used on each data line.

ADL5240ACPZ-R7 数据表(PDF) 17 Page - Analog Devices

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